International Journal of Innovative Research and Development

Abstract

This brief proposes a low power and area efficient linear phase FIR digital filter of odd length using improved carry select adder (CSLA). The proposed parallel FIR architecture exploits the advantages of symmetric coefficient and reduces the number of multipliers in the sub filter section at the expense of increase in adders in preprocessing and post processing blocks using fast FIR algorithm. As the length of the FIR filter increases the number of reduced multipliers increase. But the increase in adders in pre/post processing blocks stays fixed.  Adders have less area than multipliers, so exchange of multipliers with adders reduces the area and power of the filter. For further area reduction an improved CSLA is used instead of a SQRT CSLA.

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