Design and Analysis of an Efficient Full Adder Using Systematic Cell Design Methodology

In this paper, a high performance and low power full adder using Systematic Cell Design Methodology (SCDM) is explained. The design is initially executed for 1 bit and afterward reached out to 4 bit too. The circuit was implemented using Mentor Graphics tools at 180 nm technology. The performance parameters like average propagation delay, average power and Power Delay Product (PDP) are compared with existing hybrid adders like SRCPL adder and DPL adder. The proposed adder has less number of transistors in the critical path leading to less propagation delay. The utilization of transmission gate all through the design guarantees high driving ability and full voltage swing at the output. The proposed adder is observed to work productively when compared with different adders in terms of average power, average propagation delay and PDP. The Schematic Driven Layout of the proposed adder is obtained using Mentor Graphics IC station and the physical verifications are done using Calibre tool.