ICTACT Journal on Microelectronics

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Design and Analysis of an Efficient Full Adder Using Systematic Cell Design Methodology


Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, India
     

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In this paper, a high performance and low power full adder using Systematic Cell Design Methodology (SCDM) is explained. The design is initially executed for 1 bit and afterward reached out to 4 bit too. The circuit was implemented using Mentor Graphics tools at 180 nm technology. The performance parameters like average propagation delay, average power and Power Delay Product (PDP) are compared with existing hybrid adders like SRCPL adder and DPL adder. The proposed adder has less number of transistors in the critical path leading to less propagation delay. The utilization of transmission gate all through the design guarantees high driving ability and full voltage swing at the output. The proposed adder is observed to work productively when compared with different adders in terms of average power, average propagation delay and PDP. The Schematic Driven Layout of the proposed adder is obtained using Mentor Graphics IC station and the physical verifications are done using Calibre tool.

Keywords

Three Input XOR/XNOR, Systematic Cell Design Methodology, Transmission Gate, Full Adder, Low Power High Performance.
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  • C.H. Chang, J. Gu and M. Zhang, “A Review of 0.18-μm Full Adder Performances for Tree Structured Arithmetic Circuits”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 13, No. 6, pp. 686-695, 2005.

  • Sumeer Goel, Ashok Kumar and Magdy A. Bayoumi, “Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 14, No. 12, pp. 1309-1321, 2006.

  • Mariano Aguirre-Hernandez and Monico Linares-Aranda, “CMOS Full-Adders for Energy-Efficient Arithmetic Applications”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 19, No. 4, pp. 718-721, 2011.

  • T. Nikoubin, A. Baniasadi, F. Eslami, and K. Navi, “A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic”, Journal of Low Power Electronics, Vol. 5, No. 4, pp. 474-483, 2009.

  • T. Nikoubin, M. Grailoo, and S. H. Mozafari, “Cell Design Methodology based on Transmission Gate for Low-Power High-Speed Balanced XOR- XNOR Circuits in Hybrid-CMOS Logic Style”, Journal of Low Power Electronics, Vol. 6, No. 4, pp. 503-512, 2010.

  • Tooraj Nikoubin, Mahdieh Grailoo and Changzhi Li, “Energy and Area Efficient Three-Input XOR/XNORs with Systematic Cell Design Methodology”, IEEE Transactions on Very Large Scale Integration Systems, Vol.24, No. 1, pp. 398-402, 2016.


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  • Design and Analysis of an Efficient Full Adder Using Systematic Cell Design Methodology

Abstract Views: 252  |  PDF Views: 0

Authors

G. Jyothish Chandran
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India
Anila Susan George
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India
Anu Raj
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India

Abstract


In this paper, a high performance and low power full adder using Systematic Cell Design Methodology (SCDM) is explained. The design is initially executed for 1 bit and afterward reached out to 4 bit too. The circuit was implemented using Mentor Graphics tools at 180 nm technology. The performance parameters like average propagation delay, average power and Power Delay Product (PDP) are compared with existing hybrid adders like SRCPL adder and DPL adder. The proposed adder has less number of transistors in the critical path leading to less propagation delay. The utilization of transmission gate all through the design guarantees high driving ability and full voltage swing at the output. The proposed adder is observed to work productively when compared with different adders in terms of average power, average propagation delay and PDP. The Schematic Driven Layout of the proposed adder is obtained using Mentor Graphics IC station and the physical verifications are done using Calibre tool.

Keywords


Three Input XOR/XNOR, Systematic Cell Design Methodology, Transmission Gate, Full Adder, Low Power High Performance.

References