ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Power and Area Efficient 10T Sram with Improved Read Stability


Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, India
     

   Subscribe/Renew Journal


In this paper, a 10T Static Random Access Memory bit cell is proposed to meet design specification for performance, stability, area and power consumption. In every state of SRAM cell designs low power and increased noise margin plays an important role. The conventional 6T SRAM cell is very much prone to noise during read operation. In order to overcome the Read SNM problem in the 6T SRAM cell designers have implemented many other SRAM configurations such as 8T, 9T, 10T. These SRAM cell configurations improve the read stability but increase the power consumption. We proposed a 10T SRAM cell which can solve all these problems by introducing the transmission gate and using stacking effect in the configuration. In this paper different SRAM cells analyzed on the basis of power and read stability and we proposed a 1-bit SRAM memory array using the proposed 10T SRAM bit cell that achieves cell stability, lower power consumption and lesser area. The proposed circuit was implemented in Mentor Graphics Design Architect, simulated using Mentor Graphics ELDO at supply voltage of 1.8V with the help of TSMC 180nm technology. Micro wind is used to draw layout of SRAM cells and peripherals.

Keywords

Static Random Access Memory, Static Noise Margin, Read Static Noise Margin, Power Consumption, 10T SRAM.
Subscription Login to verify subscription
User
Notifications
Font Size

  • Vasudha Gupta and Mohab Anis, “Statistical Design of the 6T SRAM Bit Cell”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 57, No. 1, pp. 93-103, 2010.

  • Evert Seevinck, Frans J.List and Jan Lohstroh, “Static Noise Margin analysis of MOS SRAM cells”, IEEE Journal of Solid-State Circuits, Vol. 22, No. 5, pp. 748-754, 1987.

  • Anantha P. Chandrakasan, Samuel Sheng and Robert W. Brodersen, “Low-Power CMOS Digital Design”, IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, pp. 473-483, 1992.

  • Satyanand Nalam and Benton H. Calhoun, “5T SRAM with Asymmetric Sizing for Improved Read Stability”, IEEE Journal of Solid-State Circuits, Vol. 46, No. 10, pp. 2437-2442, 2011.

  • C.B. Kushwah and S.K. Vishvakarma, “A Single Ended with Dynamic Feedback Control 8T Subthreshold SRAM Cell”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 1, pp. 373-377, 2016.

  • Vasudha Gupta and Mohab Anis, “Statistical Design of the 6T SRAM Bit Cell”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 57, No. 1, pp. 93-104, 2010.

  • Benton H. Calhoun and Anatha P. Chandrakasan, “Static Noise Margin variation for sub-threshold SRAM in 65nm CMOS”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 41, No. 7, pp. 1673-1679, 2006.

  • K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii and H. Kobatake, “A Read Static Noise Margin Free SRAM Cell for Low VDD and High Speed Applications”, IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, pp. 113-121, 2006.

  • Hiroyuki Yamauchi, “A Discussion on SRAM Circuit Design Trend in Deeper Nanometer- Scale Technologies”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 18, No. 5, pp. 763-773, 2010.

  • Do Anh-Tuan, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan and Kiat-Seng Yeo, “A 8T Differential SRAM with Improved Noise Margin for Bit-Interleaving in 65nm CMOS”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 58, No. 6, pp. 1252-1263, 2011.

  • Kiat-Seng Yeo and Kaushik Roy, “Low- Voltage, Low- Power VLSI Subsystems”, 1st Edition, Mc Graw-Hill, 2009.


Abstract Views: 249

PDF Views: 1




  • Power and Area Efficient 10T Sram with Improved Read Stability

Abstract Views: 249  |  PDF Views: 1

Authors

T. S. Geethumol
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India
K. S. Sreekala
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India
P. B. Dhanusha
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India

Abstract


In this paper, a 10T Static Random Access Memory bit cell is proposed to meet design specification for performance, stability, area and power consumption. In every state of SRAM cell designs low power and increased noise margin plays an important role. The conventional 6T SRAM cell is very much prone to noise during read operation. In order to overcome the Read SNM problem in the 6T SRAM cell designers have implemented many other SRAM configurations such as 8T, 9T, 10T. These SRAM cell configurations improve the read stability but increase the power consumption. We proposed a 10T SRAM cell which can solve all these problems by introducing the transmission gate and using stacking effect in the configuration. In this paper different SRAM cells analyzed on the basis of power and read stability and we proposed a 1-bit SRAM memory array using the proposed 10T SRAM bit cell that achieves cell stability, lower power consumption and lesser area. The proposed circuit was implemented in Mentor Graphics Design Architect, simulated using Mentor Graphics ELDO at supply voltage of 1.8V with the help of TSMC 180nm technology. Micro wind is used to draw layout of SRAM cells and peripherals.

Keywords


Static Random Access Memory, Static Noise Margin, Read Static Noise Margin, Power Consumption, 10T SRAM.

References