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Power Efficient High Speed Adaptive Biased Operational Amplifier


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1 Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, India
     

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This paper presents a new adaptive biasing technique for improving the slew rate of CMOS opamps without increasing the power consumption. All the proposed circuits for adaptive biasing are implemented using a current subtractor and NMOS based circuit. Further, the input stage of opamp in proposed circuits were substituted by Flipped Voltage Follower circuit and Self Cascode structure to study their effects on adaptive biasing circuits. The conclusion of this work is that there is a notable enhancement in slew rate, settling time and power dissipation in proposed adaptive biasing techniques. All the circuits have been designed using 180nm CMOS technology and simulated using cadence virtuoso.

Keywords

Adaptive Biasing, Opamp, Slew Rate, Flipped Voltage Follower, Self Cascode, Power Dissipation.
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  • M.W. Rashid, Annajirao Garimella and Paul M. Furth, “An Adaptive Biasing Technique to Convert a Pseudo-Class AB Amplifier to Class AB”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 57, No. 4, pp. 250-254, 2010.
  • Siddhartha, Gopal Krishna and B.J. Farahani, “A Fast Settling Slew Rate Enhancement Technique for Operational Amplifiers”, Proceedings of 53rd IEEE International Midwest Symposium on Circuits and Systems, pp. 203-214, 2010.
  • S. Baswa, A.J. Lopez-Martin, R.G. Carvajal and J. Ramirez-Angulo, “Low-Voltage Power Efficient Adaptive Biasing for CMOS Amplifiers and Buffers”, Electronics Letters, Vol. 40, No. 4, pp. 217-219, 2004.
  • G. Ferri, V. Stornelli, Andrea De Marcellis and Angelo Celeste, “A rail-to-rail DC-Enhanced Adaptive Biased Fully Differential OTA”, Proceedings of IEEE 18th European Conference on Circuit Theory and Design, pp. 527-530, 2007.
  • Tuan Vu Cao and Dag T. Wisland, “Rail-to- Rail Low-Power Fully Differential OTA Utilizing Adaptive Biasing and Partial Feedback”, Proceedings of IEEE International Symposium on Circuits and Systems, pp. 30-36, 2010.
  • J. Torfifard and A.K. Bin Aain, “A Power-Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier”, ETRI Journal, Vol. 35, No. 2, pp. 226-233, 2013.
  • Toshihiro Ozaki, Tetsuya Hirose and Keishi Tsubaki, “A Nano-Watt Power Rail-to- Rail CMOS Amplifier with Adaptive Biasing for Ultra-Low Power Analog LSIs”, Proceedings of International Conference on Solid State Devices and Materials, pp. 1-6, 2014.
  • Akbari Meysam et al., “Employing Adaptive-Biasing Technique and New Drivers to Upgrade Folded Cascode Amplifiers”, Proceedings of International Conference on Advances and Innovations in Engineering, pp. 12-18, 2018.
  • Hamid Abolfazli Ghamsari and Mahdi Pirmoradian, “Adaptive Biasing Low Power Amplifier using CMOS Technology”, Journal of Applied Sciences, Vol. 15, pp. 1256-1260, 2015.
  • V. Stornelli, L. Pantoli and G. Ferri, “The AB-CCII, A Novel Adaptive Biasing LV-LP Current Conveyor Architecture”, AEU-International Journal of Electronics and Communications, Vol. 79, pp. 301-306, 2017.
  • A. Singh, S. Soni, V. Niranjan and A. Kumar, “Slew Rate Enhancement”, Proceedings of International Conference on Advances in Computing, Communication Control and Networking, pp. 293-299, 2018.

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  • Power Efficient High Speed Adaptive Biased Operational Amplifier

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Authors

Nimeesha
Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, India
Shikha Soni
Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, India
Vandana Niranjan
Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, India
Ashwni Kumar
Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, India

Abstract


This paper presents a new adaptive biasing technique for improving the slew rate of CMOS opamps without increasing the power consumption. All the proposed circuits for adaptive biasing are implemented using a current subtractor and NMOS based circuit. Further, the input stage of opamp in proposed circuits were substituted by Flipped Voltage Follower circuit and Self Cascode structure to study their effects on adaptive biasing circuits. The conclusion of this work is that there is a notable enhancement in slew rate, settling time and power dissipation in proposed adaptive biasing techniques. All the circuits have been designed using 180nm CMOS technology and simulated using cadence virtuoso.

Keywords


Adaptive Biasing, Opamp, Slew Rate, Flipped Voltage Follower, Self Cascode, Power Dissipation.

References