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Comparative Analysis of Pulse Triggered Flip Flop Design for Low Power Consumption
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The advancement in the field of CMOS technology has motivated the research to implement more and more complicated signal processing systems on a Very Large Scale Integrated (VLSI) chip. The basic requirements of such CMOS units are to consume less power and have more functionality. The chip area, speed and power consumption are considered to be the main criteria for evaluating the quality of the systems performance. Hence, there are many types of flip flops designed based on their operation like master and slave based flip flop, conventional transmission gate flip flop and pulse triggered based flip flop. This paper, presents a different methodology using pulse triggered instead of flip flop without altering the existing design style. In this design a pulse triggered flip flop is preferred and then compared with Modified Hybrid Latch Flip Flop (MHLFF), Explicit Pulse Double Edge Triggered Flip Flop (ep-DETFF) and Adaptive Coupling Configured Flip Flop (ACFF). All the proposed flip flops have been designed using 90 nm CMOS technology and their functionality has been verified using micro wind/Dsch2 tool. From this work, the parameters like layout size, transistor count, delay and power are analyzed and compared based on the different types of flip flops. Finally, it is proved that low power Pulse triggered Flip Flop is ACFF.
Keywords
Flip-Flop, Pulse Triggered Latch, Modified Hybrid Latch Flip Flop, Adaptive Coupling Configured Flip Flop, Explicit Pulse Double Edge Triggered Flip Flop.
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