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Comparative Analysis of Pulse Triggered Flip Flop Design for Low Power Consumption
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The advancement in the field of CMOS technology has motivated the research to implement more and more complicated signal processing systems on a Very Large Scale Integrated (VLSI) chip. The basic requirements of such CMOS units are to consume less power and have more functionality. The chip area, speed and power consumption are considered to be the main criteria for evaluating the quality of the systems performance. Hence, there are many types of flip flops designed based on their operation like master and slave based flip flop, conventional transmission gate flip flop and pulse triggered based flip flop. This paper, presents a different methodology using pulse triggered instead of flip flop without altering the existing design style. In this design a pulse triggered flip flop is preferred and then compared with Modified Hybrid Latch Flip Flop (MHLFF), Explicit Pulse Double Edge Triggered Flip Flop (ep-DETFF) and Adaptive Coupling Configured Flip Flop (ACFF). All the proposed flip flops have been designed using 90 nm CMOS technology and their functionality has been verified using micro wind/Dsch2 tool. From this work, the parameters like layout size, transistor count, delay and power are analyzed and compared based on the different types of flip flops. Finally, it is proved that low power Pulse triggered Flip Flop is ACFF.
Keywords
Flip-Flop, Pulse Triggered Latch, Modified Hybrid Latch Flip Flop, Adaptive Coupling Configured Flip Flop, Explicit Pulse Double Edge Triggered Flip Flop.
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- David John Willingham, “Asynchrobatic Logic for Low-Power VLSI Design”, PhD Dissertation, University of Westminster, 2010.
- Sakshi Goyal, Gurvinder Singh and Pushpinder Sharma, “Power Dissipation Analysis of Conventional CMOS and Adiabatic CMOS Circuits”, International Journal of Emerging Technologies in Computational and Applied Sciences, Vol. 2, No. 3, pp. 254-258, 2014.
- Baljinder Kaur, Narinder Sharma, and Gurpreet Kaur, “An Efficient Adiabatic Full Adder Design Approach for Low Power”, International Journal of Advance Research in Science and Engineering, Vol. 5, No. 5, pp. 22-28, 2016.
- Yong Moon and Deog-Kyoon Jeong, “An Efficient Charge Recovery Logic Circuit”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 4, pp. 121-128, 1996.
- K.A. Valiev and V.I. Staroselskii, “A Model and Properties of a Thermodynamically Reversible Logic Gate”, Mikroelektronika, Vol. 29, No. 2, pp. 83-98, 2000.
- D.R. Premchand and B. Siddlingamma, “Power Analysis of CMOS and Adiabatic Logic Design”, Proceedings of 7th IRF International Conference, pp. 5-9, 2014.
- S. Amalin Marina, T. Shunbaga Pradeepa and A. Rajeswari ‘‘Analysis of Full Adder using Adiabatic Charge Recovery Logic”, Proceedings of International Conference on Circuit, Power and Computing Technologies, pp. 1-7, 2016.
- B. Dilli Kumar and M. Barathi, “Design of Energy Efficient Arithmetic Circuits using Charge Recovery Adiabatic Logic”, International Journal of Engineering Trends and Technology, Vol. 4, No. 1, pp. 32-40, 2013.
- D. Jayanthi, A. Bhavani Shankar, S. Raghavan and G. Rajasekar, “High Speed Multi Output Circuits using Adiabatic Logic”, Proceedings of International Conference on Emerging Trends in Engineering, Technology and Science, 2016.
- Akansha Maheshwari and Surbhit Luthra, “Low Power Full Adder Circuit Implementation using Transmission Gate”, International Journal of Advanced Research in Computer and Communication Engineering, Vol. 4, No. 7, pp. 183-185, 2015.
- V. Stojanovic and V. Oklobdzija, “Comparative Analysis of Master Slave Latches and Flip-Flops for High-Performance and Low-Power Systems”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 4, pp. 536-548, 1999.
- J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev and V. De, “Comparative Delay and Energy of Single Edge-Triggered and Dual Edge Triggered Pulsed Flip-Flops for High-Performance Microprocessors”, Proceedings of International Symposium on Low Power Electronics and Design, pp. 207-212, 2001.
- P. Zhao, T. Darwish and M. Bayoumi, “High-Performance and Low Power Conditional Discharge Flip-Flop”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 12, No. 5, pp. 477-484, 2004.
- Y.T. Hwang, J.F. Lin and M.H. Sheu, “Low Power Pulse Triggered Flip-Flop Design with Conditional Pulse Enhancement Scheme”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 20, No. 2, pp. 361-366, 2012.
- S.H. Rasouli, A. Khademzadeh, A. Afzali-Kusha and M. Nourani, “Low Power Single and Double-Edge-Triggered Flip-Flops for High Speed Applications”, IEE Proceedings-Circuits, Devices and Systems, Vol. 152, No. 2, pp. 118-122, 2005.
- J.F. Lin, “Low-Power Pulse-Triggered Flip-Flop Design based on a Signal Feed-Through Scheme”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 22, No. 1, pp. 181-185, 2014.
- A.S. Seyeidi and A. Afzalui-Kusha, “Double-Edge Triggered Level Convertor Flip-Flop with Feedback”, Proceedings of International Conference on Microelectronics, pp. 44-47, 2006.
- M.W. Phyu, W.L. Goh and K.S. Yeo, “A Low-Power Static Dual Edge Triggered Flip-Flop using an Output-Controlled Discharge Configuration”, Proceedings of IEEE International Symposium on Circuits and Systems, pp. 125-128, 2014.
- Ashish Kumar, Yogendera Kumar and Deepak Berwal, “Low Power Dual Edge Triggered Flip Flop using Multi Threshold CMOS”, Proceedings of International Conference on Computing, Communication and Automation, pp. 1358-1360, 2016.
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