ICTACT Journal on Microelectronics

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FPGA Implementation of SSPA Decoder


Affiliations
1 Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, India
2 Department of Electronics and Communication Engineering, Dayananda Sagar Academy of Technology and Management, India
3 Department of Electronics and Communication Engineering, BMS College of Engineering, India
     

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SSPA decoder is one of the efficient coding techniques that belongs to LDPC codes. LDPC codes are gaining greater importance in the applications requiring efficient and reliable transfer of information over communication channel. LDPC codes are innovative techniques which play a significant role in satellite communication, CDMA, Bluetooth etc. where the main purpose is to achieve the reliable data transmission maintaining efficiency, quality and minimum bandwidth. Thus, in the present paper, an effort is made on FPGA implementation of LDPC decoding algorithm using Simplified Sum Product Algorithm (SSPA) technique to obtain better efficiency with lesser error rate. The SSPA algorithm is verified in MATLAB for different parity check matrix combinations. Then this is coded in HDL and implemented in real time, integrating with FPGA using Artix-7.

Keywords

Sum Product Algorithm (SPA), Simplified Sum Product Algorithm (SSPA), Low Density Parity Check (LDPC), Variable Node (VN), Check Node (CN).
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  • FPGA Implementation of SSPA Decoder

Abstract Views: 250  |  PDF Views: 0

Authors

A. Rajagopal
Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, India
K. Karibasappa
Department of Electronics and Communication Engineering, Dayananda Sagar Academy of Technology and Management, India
K. S. Vasundara Patel
Department of Electronics and Communication Engineering, BMS College of Engineering, India

Abstract


SSPA decoder is one of the efficient coding techniques that belongs to LDPC codes. LDPC codes are gaining greater importance in the applications requiring efficient and reliable transfer of information over communication channel. LDPC codes are innovative techniques which play a significant role in satellite communication, CDMA, Bluetooth etc. where the main purpose is to achieve the reliable data transmission maintaining efficiency, quality and minimum bandwidth. Thus, in the present paper, an effort is made on FPGA implementation of LDPC decoding algorithm using Simplified Sum Product Algorithm (SSPA) technique to obtain better efficiency with lesser error rate. The SSPA algorithm is verified in MATLAB for different parity check matrix combinations. Then this is coded in HDL and implemented in real time, integrating with FPGA using Artix-7.

Keywords


Sum Product Algorithm (SPA), Simplified Sum Product Algorithm (SSPA), Low Density Parity Check (LDPC), Variable Node (VN), Check Node (CN).