VLSI Architecture for Error Detection and Correction Based on XOR Against Multiple Cell Upsets with Reduced Redundant Bits

Memories are in general protected with error correction codes per word in order to improve its reliability. The errors introduced by the radiation particles on memories will affect more than one cell leading to what is called as Multiple Cell Upsets (MCUs). As technology is scaled down, MCUs become a more problematic one in SRAM memory, because MCUs flip the logical state in memory thereby affecting its reliability by introducing errors. The existing Error Correction Codes (ECC) such as Matrix Code (MC), Punctured Difference Set code (PDS) and Decimal Matrix Code (DMC) are lagging in the number of bits that it can correct and also it utilizes more redundant bits for detection. Hence for detecting and correcting the consecutive errors as well as for reducing the redundant bits, we propose here VLSI architecture based on a simple XOR operation over the least significant bits. It is understood from the simulation analysis that the proposed architecture achieves low area, power, and delay with an improved capability of error correction and detection. The proposed design results in twice the number of corrected errors as that of DMC.