Design of Carry Dependent Sum Adder using Reversible Logic

Low power is a paramount concern in the design of ‘digital signal processor’ (DSP) for future multimedia applications. The quest to achieve low power has made the researchers to look into different techniques. In more recent years, the reversible logic is emerged as an alternate and promising low power technique for next generation technologies. It finds vast applications in nanotechnology, low power CMOS circuit design, approximate computing, optical computing, and quantum computing etc. The full adder being critical element of DSP plays an important role in the contribution of overall power of the system under consideration. This paper proposes a design of novel reversible full adder based on ‘carry-dependent sum full adder’ (CSFA) architecture using the standard reversible logic gates. The proposed reversible FA herein referred to as ‘Reversible CSFA’ (RCSFA). Two variants of RCSFA namely RCSFA-1 and RCSFA-2 have been proposed and discussed. To assess the merits of proposed RCSFAs, they are compared against the state-of-the-art reversible full adders (RFAs) in terms of quantum gate metrics (QGMs) such as number of gates, ‘quantum cost’ (QC), constant inputs, and garbage outputs etc. From the comparison results the proposed RCSFAs are found to be an alternative choice for designers in terms of QC, constant inputs and garbage outputs.