ICTACT Journal on Microelectronics

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Design of 1kB SRAM Array Using Enhanced Stability 10t SRAM Cell for FPGA Based Applications


Affiliations
1 Department of Electronics and Communication Engineering, Andhra University College of Engineering, India
     

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SRAM used for the FPGA, requires higher stability and low power consumption. 8T SRAM cell has degraded write stability with the decreasing supply voltages. 10T SRAM cell has higher write stability because of the cut-off switch employed in the pull-up path in one of the inverters. The design of SRAM array with low power consumption and higher stability is of major importance. So, 1Kb SRAM array using 8T and 10T SRAM cells has been designed and compared for different design metrics. Write 0 and Write 1 power is lower by 1.98×, 3.52× in 10T SRAM Array than 8T SRAM Array at 0.9VDD, SS corner. Due to the usage of High-Vth transistors in 10T SRAM cell, the Read power is lower by 1.6× than 8T SRAM Array for 0.9V VDD at SS Corner. The leakage power while holding 0 is lower by 1.13× in 10T SRAM array than 8T SRAM array at FF corner at 0.9V VDD. The design metrics are evaluated for a wide range of supply voltage. The designs are implemented in Cadence Virtuoso in 45nm Technology node.

Keywords

SRAM Peripherals, Power, Delay.
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  • Design of 1kB SRAM Array Using Enhanced Stability 10t SRAM Cell for FPGA Based Applications

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Authors

R. Manoj Kumar
Department of Electronics and Communication Engineering, Andhra University College of Engineering, India
P. V. Sridevi
Department of Electronics and Communication Engineering, Andhra University College of Engineering, India

Abstract


SRAM used for the FPGA, requires higher stability and low power consumption. 8T SRAM cell has degraded write stability with the decreasing supply voltages. 10T SRAM cell has higher write stability because of the cut-off switch employed in the pull-up path in one of the inverters. The design of SRAM array with low power consumption and higher stability is of major importance. So, 1Kb SRAM array using 8T and 10T SRAM cells has been designed and compared for different design metrics. Write 0 and Write 1 power is lower by 1.98×, 3.52× in 10T SRAM Array than 8T SRAM Array at 0.9VDD, SS corner. Due to the usage of High-Vth transistors in 10T SRAM cell, the Read power is lower by 1.6× than 8T SRAM Array for 0.9V VDD at SS Corner. The leakage power while holding 0 is lower by 1.13× in 10T SRAM array than 8T SRAM array at FF corner at 0.9V VDD. The design metrics are evaluated for a wide range of supply voltage. The designs are implemented in Cadence Virtuoso in 45nm Technology node.

Keywords


SRAM Peripherals, Power, Delay.

References