ICTACT Journal on Microelectronics

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Designing of Variations Tolerant Sensing Amplifier Circuit for Deep Sub-Micron Memories


Affiliations
1 Department of Electronics and Communication Engineering, Sant Longowal Institute of Engineering and Technology, India
2 Department of Electrical and Instrumentation Engineering, Sant Longowal Institute of Engineering and Technology, India
     

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In deep sub-micron memories like DRAM and SRAM, faithful sensing of bit line voltages is becoming very challenging as transistor characteristics mismatch caused by intrinsic variations in manufacturing processes has posed a grave challenge leading to failures of circuits and reductions in yield. This paper addressed these issues and applied a compensation scheme to various schematics of sense amplifiers, which have resulted in a high tolerance to process-induced variations. The schematics, designed with DGFinFET, utilize an enhanced self-compensation technique to surmount disparities in physical transistor characteristics. The recreations of transistor mismatch (threshold voltage, Vt) using the Monte-Carlo technique show that the proposed CCLSA schematic performs correctly even for severe Vt mismatch of 40-50mV. These results are compared with corresponding circuits reported in the literature for the speed, area, and yield. This design also offers up to 20-30 % higher yield compared to its uncompensated counterpart and has a reduced penalty for the complexity of circuit and performance. These circuits are easily implementable at 45nm and 32nm technology nodes.

Keywords

Compensation, Process Variations, DRAM, FinFET Sense Amplifier, Robustness.
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  • S.S. Rathod, A.K. Saxena and S. Dasgupta, “A Low-Noise, Process-Variation-Tolerant Double-Gate FinFET based Sense Amplifier”, Microelectronics Reliability, Vol. 51, No. 4, pp. 773-780, 2011.

  • B.S. Reniwal, P. Bhatia and S.K. Vishvakarma, “Design and Investigation of Variability Aware Sense Amplifier for Low Power, High Speed SRAM”, Microelectronics, Vol. 59, pp. 22-32, 2017.

  • R. Sharma, A. Mowar and A. Johari, “Comparison of Transients and FFT Memory Sense Amplifiers for Semiconductor Memories using 0.3μm CMOS Technology”, Proceedings of International Conference on Advanced Computation and Telecommunication, pp. 1-7, 2018.

  • E. Oriero and S.R. Hasan, “Survey on Recent Counterfeit IC Detection Techniques and Future Research Directions”, Integration, Vol. 66, pp. 135-152, 2019.

  • Bin Yu, “FinFET Scaling to 10nm Gate Length”, Proceedings of International Meeting on Electron Devices, pp. 251-252, 2002.

  • E. J. Nowak, “Scaling Beyond the 65 nm Node with FinFET-DGCMOS”, Proceedings of International Conference on Custom Integrated Circuits, pp. 339-342, 2003.

  • K. Itoh, Y. Nakagome, S. Kimura and T. Watanabe, “Limitations and Challenges of Multigigabit DRAM Chip Design”, IEEE Journal on Solid-State Circuits, Vol. 32, pp. 624-634, 1997.

  • T. Yamagata, S. Tomishima, M. Tsukude, Y. Hashizume, and K. Arimoto, “Circuit Design Techniques for Low-Voltage Operating and/or Giga-Scale DRAMs”, Proceedings of International Conference on Solid-State Circuits, pp. 248-254, 1995.

  • J.A. Mandelman, “Challenges and Future Directions for the Scaling of Dynamic Random-Access Memory (DRAM)”, IBM Journal of Research and Development, Vol. 46, No. 2-3, pp. 2-6, 2002.

  • PTM, “Latest Model”, Available at http://www.eas.asu.edu/~ptm/, Accessed at 2012.

  • S. Mukhopadhyay, H. Mahmoodi and K. Roy, “A Novel High-Performance and Robust Sense Amplifier using Independent Gate Control in Sub-50-nm Double-Gate MOSFET”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 2, pp. 183-192, 2006.

  • J. Yeung and Hamid Mahmoodi, “Robust Sense Amplifier Design under Random Dopant Fluctuations in Nanoscale CMOS Technologies”, Proceedings of IEEE International Conference on System on Chip, pp. 261-264, 2006.

  • S. Mukhopadhyay, A. Raychowdhury, H. Mahmoodi and K. Roy, “Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM”, Proceedings of 14th Asian Test Symposium, pp. 176-181, 2005.

  • Aarti Choudhary and Sandip Kundu, “A Process Variation Tolerant Self-Compensating FinFET based Sense Amplifier Design”, Proceedings of the 19th ACM Great Lakes symposium on VLSI, pp. 161-164, 2009.

  • Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, “Digital Integrated Circuits-A Design Perspective”, 2nd Edition, Prentice Hall, 2006.

  • P. Pranav, B. Giraud and A. Amara, “An Innovative Ultra Low Voltage Sub-32nm SRAM Voltage Sense Amplifier in DG-SOI Technology”, Proceedings of International Conference on Circuits and Systems, pp. 205-208, 2008.

  • B. Wicht, T. Nirschl and D. Schmitt-Landsiedel, “Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 7, pp. 1148-1158, 2004.

  • A. Datta, A. Goel, R.T. Cakici, H. Mahmoodi, D. Lekshmanan and K. Roy, “Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 11, pp. 1957-1966, 2007.

  • D. Nagamani, B.K.V Prasad, K.J.S. Lorraine and B.V.V.S. Kumar, “Fault Diagnosis of a Sense Amplifier Circuit”, Procedia Engineering, Vol. 30, pp. 937-944, 2012.


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  • Designing of Variations Tolerant Sensing Amplifier Circuit for Deep Sub-Micron Memories

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Authors

Vivek Harshey
Department of Electronics and Communication Engineering, Sant Longowal Institute of Engineering and Technology, India
S. K. Bansal
Department of Electrical and Instrumentation Engineering, Sant Longowal Institute of Engineering and Technology, India

Abstract


In deep sub-micron memories like DRAM and SRAM, faithful sensing of bit line voltages is becoming very challenging as transistor characteristics mismatch caused by intrinsic variations in manufacturing processes has posed a grave challenge leading to failures of circuits and reductions in yield. This paper addressed these issues and applied a compensation scheme to various schematics of sense amplifiers, which have resulted in a high tolerance to process-induced variations. The schematics, designed with DGFinFET, utilize an enhanced self-compensation technique to surmount disparities in physical transistor characteristics. The recreations of transistor mismatch (threshold voltage, Vt) using the Monte-Carlo technique show that the proposed CCLSA schematic performs correctly even for severe Vt mismatch of 40-50mV. These results are compared with corresponding circuits reported in the literature for the speed, area, and yield. This design also offers up to 20-30 % higher yield compared to its uncompensated counterpart and has a reduced penalty for the complexity of circuit and performance. These circuits are easily implementable at 45nm and 32nm technology nodes.

Keywords


Compensation, Process Variations, DRAM, FinFET Sense Amplifier, Robustness.

References