ICTACT Journal on Microelectronics

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Design and Development of SOC Based Network on Chip Topologies


Affiliations
1 Department of Electronics and Communication Engineering, Osmania University, India
2 Department of Electronics and Communication Engineering, Vasavi College of Engineering, India
     

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The submicron technologies are revealing problems in the interconnections. Thus, the performance of the system largely depends on the structure of communication, in particular with regard to the flow, surface area and power consumed. In addition, traditional communications structures, which are generally based on shared buses, are limited in terms of performance. Indeed, they do not support high flow rates and they do not allow many elements to be interconnected, which makes them not very extensible. Based on this observation, several research groups have worked on a new form of interconnection adapted to future even more complex systems on a chip. They proposed the paradigm of networks on chip. In this paper, various SoC based network topologies has been implemented. Among various network topologies, the four well known topologies are selected. These selected four topologies are implemented by using Verilog programming language and corresponding results has been discussed.

Keywords

Network on Chip, Network Topologies, System on Chip, FPGA.
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  • Design and Development of SOC Based Network on Chip Topologies

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Authors

T. Nagalaxmi
Department of Electronics and Communication Engineering, Osmania University, India
E. Sreenivasa Rao
Department of Electronics and Communication Engineering, Vasavi College of Engineering, India
P. Chandrasekhar
Department of Electronics and Communication Engineering, Osmania University, India

Abstract


The submicron technologies are revealing problems in the interconnections. Thus, the performance of the system largely depends on the structure of communication, in particular with regard to the flow, surface area and power consumed. In addition, traditional communications structures, which are generally based on shared buses, are limited in terms of performance. Indeed, they do not support high flow rates and they do not allow many elements to be interconnected, which makes them not very extensible. Based on this observation, several research groups have worked on a new form of interconnection adapted to future even more complex systems on a chip. They proposed the paradigm of networks on chip. In this paper, various SoC based network topologies has been implemented. Among various network topologies, the four well known topologies are selected. These selected four topologies are implemented by using Verilog programming language and corresponding results has been discussed.

Keywords


Network on Chip, Network Topologies, System on Chip, FPGA.

References