ICTACT Journal on Microelectronics

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FPGA Implementation of CSD Based NN Image Compression Architecture


Affiliations
1 Department of Electronics and Communication Engineering, PVKK Institute of Technology, India
2 Department of Electrical Engineering, Indian Institute of Technology, Patna, India
3 Department of Electronics and Communication Engineering, Yogi Vemana University, India
     

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Complexity will be the critical issue in Very Large Scale Integration (VLSI) implementation of Image Compression Architectures. Especially it will be predominant issue while dealing with Neural Network (NN) based image compression architectures. Due to the development of Field-Programmable Gated Array (FPGA), dealing of NN Image Compression Architecture becomes smoother. Furthermore reducing power consumption of those architectures can be deal with Canonic Signed Digit (CSD) algorithms. NN based compression can be added to standard JPEG compression is proved be an efficient strategy for dealing images of high resolution in terms of speed and power. CSD algorithm is proved to provide low power consumption along with low computation time while dealing NN structures. The proposed architecture is hence based on CSD Floating Point Matrix Multiplier (FPMM) and it is synthesized and implemented using Xilinx Vivado Artix7 and Nexys DDR boards. Simulation with MATLAB & Xilinx Vivado is carried out for this work and almost same results are observed.

Keywords

CSD, FPMM, DDR, FPGA.
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  • FPGA Implementation of CSD Based NN Image Compression Architecture

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Authors

M. Lakshmi Kiran
Department of Electronics and Communication Engineering, PVKK Institute of Technology, India
K. Nikhileswar
Department of Electrical Engineering, Indian Institute of Technology, Patna, India
K. Venkata Ramanaiah
Department of Electronics and Communication Engineering, Yogi Vemana University, India

Abstract


Complexity will be the critical issue in Very Large Scale Integration (VLSI) implementation of Image Compression Architectures. Especially it will be predominant issue while dealing with Neural Network (NN) based image compression architectures. Due to the development of Field-Programmable Gated Array (FPGA), dealing of NN Image Compression Architecture becomes smoother. Furthermore reducing power consumption of those architectures can be deal with Canonic Signed Digit (CSD) algorithms. NN based compression can be added to standard JPEG compression is proved be an efficient strategy for dealing images of high resolution in terms of speed and power. CSD algorithm is proved to provide low power consumption along with low computation time while dealing NN structures. The proposed architecture is hence based on CSD Floating Point Matrix Multiplier (FPMM) and it is synthesized and implemented using Xilinx Vivado Artix7 and Nexys DDR boards. Simulation with MATLAB & Xilinx Vivado is carried out for this work and almost same results are observed.

Keywords


CSD, FPMM, DDR, FPGA.

References