ICTACT Journal on Microelectronics

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Robust and Scalable Hybrid 1-Bit Full Adder Circuit for VLSI Applications


Affiliations
1 Department of Electronics and Communication Engineering, Vemana Institute of Technology, India
     

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This research paper presents a novel 22-transistors (22T), 1-bit ‘full-adder’ (FA) for ‘Very-large-scale-integration’ (VLSI) applications. The proposed FA is derived from the hybrid logic, which is a combination of ‘gate-diffusion-input’ (GDI) technique, ‘transmission gate’ (TG) and ‘static CMOS’ (SCMOS) logic. To assess the performance of the proposed FA, it is compared with state-of-the-art FAs in terms of ‘Design Metrics’ (DMs) such as power, delay, ‘power-delay-product’ (PDP), and ‘transistor count’ (TC). For a fair comparison, all FAs under consideration have been designed and simulated under common ‘process-voltage-temperature’ (PVT) conditions. The simulations have been conducted using Cadences’ Spectre simulator using 45 nm ‘predictive-technology-model’ (PTM). The simulations indicate that the proposed FA dissipates an ‘average power dissipation’ (APD) of 1.21 μW at an input signal frequency, fin=200 MHz and supply voltage, Vdd=1 V. It has a ‘worst case delay’ (WCD) of 135 ps and has a ‘power-delay-product’ (PDP) =0.163 fJ. Further to assess the scalability the proposed FA in terms of Vdd and input signal operand size, it is embedded in 64-bit(64b) ‘ripple carry adder’ (RCA) chain and simulations were conducted by scaling down the Vdd from 1.2 V to 0.4 V in steps of 0.2 V. The simulation results show that, only the proposed FA and other 2 reported as have the ability to operate in 64b RCA under different values of Vdd, without using any intermediate buffers. Further, it is observed that the proposed FA has a better power, delay, and TC as compared to the other 2 FAs.

Keywords

Full Adder, PDP, Low Power, Static CMOS, Gate-Diffusion-Input, Transmission-Gate-Logic.
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  • Robust and Scalable Hybrid 1-Bit Full Adder Circuit for VLSI Applications

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Authors

M. C. Parameshwara
Department of Electronics and Communication Engineering, Vemana Institute of Technology, India

Abstract


This research paper presents a novel 22-transistors (22T), 1-bit ‘full-adder’ (FA) for ‘Very-large-scale-integration’ (VLSI) applications. The proposed FA is derived from the hybrid logic, which is a combination of ‘gate-diffusion-input’ (GDI) technique, ‘transmission gate’ (TG) and ‘static CMOS’ (SCMOS) logic. To assess the performance of the proposed FA, it is compared with state-of-the-art FAs in terms of ‘Design Metrics’ (DMs) such as power, delay, ‘power-delay-product’ (PDP), and ‘transistor count’ (TC). For a fair comparison, all FAs under consideration have been designed and simulated under common ‘process-voltage-temperature’ (PVT) conditions. The simulations have been conducted using Cadences’ Spectre simulator using 45 nm ‘predictive-technology-model’ (PTM). The simulations indicate that the proposed FA dissipates an ‘average power dissipation’ (APD) of 1.21 μW at an input signal frequency, fin=200 MHz and supply voltage, Vdd=1 V. It has a ‘worst case delay’ (WCD) of 135 ps and has a ‘power-delay-product’ (PDP) =0.163 fJ. Further to assess the scalability the proposed FA in terms of Vdd and input signal operand size, it is embedded in 64-bit(64b) ‘ripple carry adder’ (RCA) chain and simulations were conducted by scaling down the Vdd from 1.2 V to 0.4 V in steps of 0.2 V. The simulation results show that, only the proposed FA and other 2 reported as have the ability to operate in 64b RCA under different values of Vdd, without using any intermediate buffers. Further, it is observed that the proposed FA has a better power, delay, and TC as compared to the other 2 FAs.

Keywords


Full Adder, PDP, Low Power, Static CMOS, Gate-Diffusion-Input, Transmission-Gate-Logic.

References