ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Comparative Evaluation and Analysis of D Flip Flop for High Speed and Low Power Applicatio


Affiliations
1 Department of Electronics and Communication Engineering, Noida International University, India
     

   Subscribe/Renew Journal


This paper presents comparative analysis of various flip-flops in CMOS technology. We simulated dual dynamic node hybrid flip flop (DDFF), Hybrid latch flip-flop (HLFF), Modified hybrid latch flip flop (MHLFF), and modified transmission gate flip flop (TGFF). The average power of various flip flops are calculated at 0%, 25%, 50% and 100% data activity, at temperature 25-100 ºC and different voltages 0.7, 0.9, 1 and 1.5. The average delay is also calculated at room temperature. All of these parameters are calculated in 32nm CMOS technology with the help of TSPICE. It was observed that MHLFF is the flop-flop that consumes less power compared to other flip flops. We are comparing performance and power dissipation and also compared transistor count of each flip flop.

Keywords

Average Power, Data Activity, Transistors, Average Delay, Edge Triggered Flip. Flop
Subscription Login to verify subscription
User
Notifications
Font Size

  • H. Patrovi, R. Burd, U. Salim, F. Weber, L. DiGregorio and D. Draper, “Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements”, Proceedings of IEEE International Conference on Digital Technology, pp. 138-139, 1996.

  • F. Klass, “Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic”, Proceedings of IEEE International Conference on Digital Technology, pp. 108-109, 1996.

  • J. Yuan and C. Svensson, “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings”, IEEE Journal on Solid-State Circuits, Vol. 32, No. 1, pp. 62-69, 1997.

  • M. Hamada, T. Terazawa, T. Higashi and T. Kuroda, “Flip-Flop Selection Technique for Power-Delay Trade-Off”, Proceedings of IEEE International Conference on Solid-State Circuits, pp. 270-271, 1999.

  • B. Nicolick, V. Stojanovic, V.G. Oklobdzija and M. Leung, “Sense Amplifier-Based Flip-Flop”, Proceedings of IEEE International Conference on Solid-State Circuits, pp. 282-283, 1999.

  • A. Shen, A. Ghosh and K. Keutzer, “On Average Power Dissipation and Random Pattern Testability of CMOS Combinational Logic Networks”, Proceedings of IEEE International Conference on Computer Aided Design, pp. 402-407, 1992.

  • A. Hertwig and H.J. Wunderlich, “Low-Power Serial Built-in Self-Test”, Proceedings of IEEE International Conference on Solid-State Circuits, pp. 49-53, 1999.

  • Peiyi Zhao, Jason B. McNeely, Pradeep K. Golconda, Soujanya Venigalla, Nan Wang, Magdy A. Bayoumi, Weidong Kuang and Luke Downey, “Low Power Clocked Pseudo NMOS Flip Flop for Level Conversion in Dual Supply Systems”, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, Vol. 17, No. 9, pp 1196-1202, 2009.

  • Kaushik Roy and Sharat Prasad, “Low Power CMOS VLSI Circuit Design”, John Wiley and Sons, 2000

  • Kalarikkal Absel, Lijo Manuel and R.K. Kavitha, “Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic”, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, Vol. 21, No. 9, pp. 1212-1219, 2013.

  • S.H. Rasouli, A. Khademzadeh, A. Afzali-Kusha and M. Nourani, “Low-Power Single and Double-Edge-Triggered Flip-Flops for High-Speed Applications”, Proceedings of International Conference on Circuits, Devices and Systems, pp. 118-122, 2005.

  • Cicero Nunes, Paulo F. Butzen, Andre I. Reis and Renato P. Ribas, “BTI, HCI and TDDB Aging Impact in Flip-Flops”, Microelectronics Reliability, Vol. 53, No. 9-11, pp. 1355-1359, 2013.

  • Shiva Taghipour and Rahebeh Niaraki Asli, “Aging Comparative Analysis of High Performance FinFET and CMOS Flip Flop”, Microelectronics Reliability, Vol. 69, No. 1, pp. 52-59, 2016.

  • Marco Lanuzza, Raffele De Rose, Fabio Frustaci, Stefania Perri and Pasquale Corsonello, “Comparative Analysis of Yield Optimized Pulsed Flip Flop”, Microelectronics Reliability, Vol. 52, No. 8, pp. 1679-1689, 2012.


Abstract Views: 195

PDF Views: 0




  • Comparative Evaluation and Analysis of D Flip Flop for High Speed and Low Power Applicatio

Abstract Views: 195  |  PDF Views: 0

Authors

Kajul Sahu
Department of Electronics and Communication Engineering, Noida International University, India
Owais Ahmad Shah
Department of Electronics and Communication Engineering, Noida International University, India

Abstract


This paper presents comparative analysis of various flip-flops in CMOS technology. We simulated dual dynamic node hybrid flip flop (DDFF), Hybrid latch flip-flop (HLFF), Modified hybrid latch flip flop (MHLFF), and modified transmission gate flip flop (TGFF). The average power of various flip flops are calculated at 0%, 25%, 50% and 100% data activity, at temperature 25-100 ºC and different voltages 0.7, 0.9, 1 and 1.5. The average delay is also calculated at room temperature. All of these parameters are calculated in 32nm CMOS technology with the help of TSPICE. It was observed that MHLFF is the flop-flop that consumes less power compared to other flip flops. We are comparing performance and power dissipation and also compared transistor count of each flip flop.

Keywords


Average Power, Data Activity, Transistors, Average Delay, Edge Triggered Flip. Flop

References