Analysis of Low Power Conditional Flip Flop in 32NM CMOS Technology for Power Constraint and Speed Sensitive Applications

In this paper, various conditional flip flops topologies are simulated in 32nm CMOS technology using BSMv4 model and compared on the basis of Power consumption, delay (Clk to Q) and Power delay Product. In Various designs of conditional flip flops, our main objective is to optimize the best design on the basis of delay and power. Simulation results showed that by using Pulse Enhancement Scheme (PES) in flip flop, power dissipation is reduced to 59.43% when compared with conditional feed through flip flop technique and further reduction of 43.34% was observed in delay at room temperature. On increasing the temperature PES technique still have less power consumption of 35.95% when compare to conditional feed through flip flop technique. It was also observed that PES technique can be used at lower voltage levels. So that dissipation and delay both reduced. In terms of delay among all designs, Single ended conditional capturing energy recovery (SCCER) has minimum delay of 2.4865ns at room temperature and 2.4843ns at 1.5V power supply. Power delay product (PDP) at room temperature of SCCER is 0.7177aJ. These results of flip flop using conditional techniques at different temperature consideration and at different voltage give us an idea to choose which scheme is better in terms of delay, power consumption and PDP.