ICTACT Journal on Microelectronics

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DESIGN OF TWO STAGE CMOS OPERATIONAL AMPLIFIER IN 180NM TECHNOLOGY WITH LOW POWER, HIGH GAIN AND HIGH SWING


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1 Department of Electronics and Communication Engineering, Dr. Rammanohar Lohia Avadh University., India
     

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For certain applications, high bandwidth operational amplifiers are required. This necessitates research into the area of op-amp bandwidth expansion without influencing any other parameters significantly. This study presents a CMOS two-stage 0perational amplifier, that operates at 1.8 V power supply in 180 nm technology and has a bias current dependent input terminal. The supply voltage has been reduced to lower the system’s overall power usage. Our primary goal is to reduce power loss, higher gain, and higher difference between maximum voltage and minimum voltage at output port. There is a trade-off between rate, power, and benefit at high supply voltages. The rate, power, and benefit of any circuit determine its performance. This op-amp has low standby power expenditure, with high driving capability, and runs at low voltage, consequential a low-power circuit. The op-amp has a gain of 70.37 decibel, a bandwidth of 53.01 MHz, and a phase margin of 27.83 degree. The operational amplifier power consumption and CMRR are also determined as 523µW and 73.33 decibel, respectively.

Keywords

Low Power, Phase Margin, CMOS, Op-Amp
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  • DESIGN OF TWO STAGE CMOS OPERATIONAL AMPLIFIER IN 180NM TECHNOLOGY WITH LOW POWER, HIGH GAIN AND HIGH SWING

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Authors

Durgesh Pratap
Department of Electronics and Communication Engineering, Dr. Rammanohar Lohia Avadh University., India
Nishant Singh
Department of Electronics and Communication Engineering, Dr. Rammanohar Lohia Avadh University., India
Shiksha Jain
Department of Electronics and Communication Engineering, Dr. Rammanohar Lohia Avadh University., India

Abstract


For certain applications, high bandwidth operational amplifiers are required. This necessitates research into the area of op-amp bandwidth expansion without influencing any other parameters significantly. This study presents a CMOS two-stage 0perational amplifier, that operates at 1.8 V power supply in 180 nm technology and has a bias current dependent input terminal. The supply voltage has been reduced to lower the system’s overall power usage. Our primary goal is to reduce power loss, higher gain, and higher difference between maximum voltage and minimum voltage at output port. There is a trade-off between rate, power, and benefit at high supply voltages. The rate, power, and benefit of any circuit determine its performance. This op-amp has low standby power expenditure, with high driving capability, and runs at low voltage, consequential a low-power circuit. The op-amp has a gain of 70.37 decibel, a bandwidth of 53.01 MHz, and a phase margin of 27.83 degree. The operational amplifier power consumption and CMRR are also determined as 523µW and 73.33 decibel, respectively.

Keywords


Low Power, Phase Margin, CMOS, Op-Amp

References