ICTACT Journal on Microelectronics

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HIGH PERFORMANCE FIR FILTER BASED ON PIPELINED PARALLEL PREFIX ADDER FOR SIGNAL PROCESSING APPLICATIONS


Affiliations
1 Department of Electronics and Communication Engineering, Vignan’s Lara Institute of Technology and Science., India
2 Department of Electronics and Communication Engineering, Vignan’s Foundation for Science, Technology and Research., India
3 Department of Electronics and Instrumentation Engineering, Kakatiya Institute of Technology and Science., India
     

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Multiple adders and multipliers make up a complex digital signal processing system (DSP). The efficient design of adders and multipliers improves the DSP system performance. In this paper, modified 4-Tap digital Finite Impulse Response (FIR) filter is built using the Pipelined Brent-Kung adder (PBKA) and a Vedic multiplier. The top-level module (FIR filter) is created by writing PBKA and PBKA-based Vedic multiplier Verilog code. The results of Pipelined Brent Kung adderbased FIR filter are compared with BKA and KSA-based 4-Tap digital FIR filter. According to the synthesis results, the PBKA-based FIR filter operates 57% faster than the BKA-based FIR filter. In terms of Power Delay Product (PDP) PBKA based FIR filter is 22% efficient than BKA based FIR filter. Xilinx 14.7 ISE software is used for simulation, while Virtex-7 FPGA is used for synthesis

Keywords

Brent Kung Adder, FIR Filter, Kogge Stone Adder, Parallel Prefix Adder, Pipelined Brent Kung Adder, Vedic Multiplier, Virtex 7 FPGA
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  • HIGH PERFORMANCE FIR FILTER BASED ON PIPELINED PARALLEL PREFIX ADDER FOR SIGNAL PROCESSING APPLICATIONS

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Authors

Basavoju Harish
Department of Electronics and Communication Engineering, Vignan’s Lara Institute of Technology and Science., India
M.S.S. Rukmini
Department of Electronics and Communication Engineering, Vignan’s Foundation for Science, Technology and Research., India
K. Sivani
Department of Electronics and Instrumentation Engineering, Kakatiya Institute of Technology and Science., India

Abstract


Multiple adders and multipliers make up a complex digital signal processing system (DSP). The efficient design of adders and multipliers improves the DSP system performance. In this paper, modified 4-Tap digital Finite Impulse Response (FIR) filter is built using the Pipelined Brent-Kung adder (PBKA) and a Vedic multiplier. The top-level module (FIR filter) is created by writing PBKA and PBKA-based Vedic multiplier Verilog code. The results of Pipelined Brent Kung adderbased FIR filter are compared with BKA and KSA-based 4-Tap digital FIR filter. According to the synthesis results, the PBKA-based FIR filter operates 57% faster than the BKA-based FIR filter. In terms of Power Delay Product (PDP) PBKA based FIR filter is 22% efficient than BKA based FIR filter. Xilinx 14.7 ISE software is used for simulation, while Virtex-7 FPGA is used for synthesis

Keywords


Brent Kung Adder, FIR Filter, Kogge Stone Adder, Parallel Prefix Adder, Pipelined Brent Kung Adder, Vedic Multiplier, Virtex 7 FPGA

References