ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

HIGH PERFORMANCE FIR FILTER BASED ON PIPELINED PARALLEL PREFIX ADDER FOR SIGNAL PROCESSING APPLICATIONS


Affiliations
1 Department of Electronics and Communication Engineering, Vignan’s Lara Institute of Technology and Science., India
2 Department of Electronics and Communication Engineering, Vignan’s Foundation for Science, Technology and Research., India
3 Department of Electronics and Instrumentation Engineering, Kakatiya Institute of Technology and Science., India
     

   Subscribe/Renew Journal


Multiple adders and multipliers make up a complex digital signal processing system (DSP). The efficient design of adders and multipliers improves the DSP system performance. In this paper, modified 4-Tap digital Finite Impulse Response (FIR) filter is built using the Pipelined Brent-Kung adder (PBKA) and a Vedic multiplier. The top-level module (FIR filter) is created by writing PBKA and PBKA-based Vedic multiplier Verilog code. The results of Pipelined Brent Kung adderbased FIR filter are compared with BKA and KSA-based 4-Tap digital FIR filter. According to the synthesis results, the PBKA-based FIR filter operates 57% faster than the BKA-based FIR filter. In terms of Power Delay Product (PDP) PBKA based FIR filter is 22% efficient than BKA based FIR filter. Xilinx 14.7 ISE software is used for simulation, while Virtex-7 FPGA is used for synthesis

Keywords

Brent Kung Adder, FIR Filter, Kogge Stone Adder, Parallel Prefix Adder, Pipelined Brent Kung Adder, Vedic Multiplier, Virtex 7 FPGA
Subscription Login to verify subscription
User
Notifications
Font Size

  • J.F. Sayed, B.H. Hasan and F. Arifin, “Design and Evaluation of a FIR Filter Using Hybrid Adders and Vedic Multipliers”, Proceedings of International Conference on Robotics, Electrical and Signal Processing Techniques, pp. 748-752, 2021.

  • P.R. Sreesh and L.S. Kumar, “Performance Analysis of Fixed Point FIR Filter Architectures”, Proceedings of 3 rd International Conference on Advances in Electronics, Computers and Communications, pp. 1-6, 2020.

  • S. Janwadkar and R. Dhavse, “Strategic Reduction of Area and Power in FIR Filter Architecture for ECG Signal Acquisition”, Proceedings of IEEE International Conference on Counil, pp. 1-7, 2020.

  • U. Maddipati, S. Ahemedali and K.N.J. Priya, “Comparative Analysis of 16-Tap FIR Filter Design using Different Adders”, Proceedings of International Conference on Computing, Communication and Networking Technologies, pp. 1-4, 2020.

  • S. Akash and N. Radha, “An Efficient Implementation of FIR Filter Using High Speed Adders for Signal Processing Applications”, Proceedings of International Conference on Inventive Research in Computing Applications, pp. 1047- 1051, 2020.

  • R.V. Arjun and K. Gayathree, “Implementation of Optimized Digital Filter using Sklansky Adder and Kogge Stone Adder”, Proceedings of International Conference on Advanced Computing and Communication Systems, pp. 661- 664, 2020.

  • B. Harish and K. Sivani, “Design and Performance Comparison among Various types of Adder Topologies”, Proceedings of International Conference on Computing Methodologies and Communication, pp. 725-730, 2020.

  • B. Harish and K. Sivani, “Design of High Speed Efficient Parallel Prefix Brent-Kung Adder Architecture”, Journal of Green Engineering, Vol. 10, No. 7, pp. 3508-3519, 2020.

  • B. Harish and K. Sivani, “Implementation of Frequency Efficient Multiplexer based CORDIC on FPGA”, International Journal of Advanced Science and Technology, Vol. 29, No. 5, pp. 753-762, 2020.

  • B. Harish and K. Sivani, “Design of MAC Unit for Digital Filters in Signal Processing and Communication”, International Journal of Speech Technology, Vol. 23, No. 1, pp.1-5, 2021.

  • B. Harish and K. Sivani, “Ultra High Speed Full Adder for Biomedical Applications”, International Journal of Reconfigurable and Embedded Systems, Vol. 10, No. 1, pp. 1-25, 2021.

  • B. Harish and K. Sivani, “Performance Comparison of Various CMOS Full Adders”, Proceedings of International Conference on Energy, Communication, Data Analytics and Soft Computing, pp. 3789-3792, 2017.

  • A.A. Wahba and H.A. Fahmy, “Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit”, IEEE Transactions on Computers, Vol. 66, No. 2, pp. 226-239, 2021.

  • A. Simson and S. Deepak, “Design and Implementation of High Speed Hybrid Carry Select Adder”, Proceedings of International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies, pp. 1-6, 2021.

  • S. Daphni and K.V. Grace, “Design an Area Efficient Kogge Stone Adder using Pass Transistor Logic”, Proceedings of International Conference on Intelligent Communication Technologies and Virtual Mobile Networks, pp. 614-618, 2021.

  • G. Thakur, H. Sohal and S. Jain, “FPGA-Based Parallel Prefix Speculative Adder for Fast Computation Application”, Proceedings of International Conference on Parallel, Distributed and Grid Computing, pp. 206-210, 2020.

  • A. Kumar, A.A. Shetty and R. Pinto, “Design and Implementation of 64-bit Parallel Prefix Adder”, Proceedings of IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics, pp. 159-164, 2020.

  • Y. Devi Ykuntam, K. Pavani and K. Saladi, “Design and Analysis of High Speed Wallace Tree Multiplier using Parallel Prefix Adders for VLSI Circuit Designs”, Proceedings of International Conference on Computing, Communication and Networking Technologies, pp. 1-6, 2020.

  • G. Thakur, H. Sohal and S. Jain, “Design and Analysis of High-Speed Parallel Prefix Adder for Digital Circuit Design Applications”, Proceedings of International Conference on Computational Performance Evaluation, pp. 95-100, 2020.

  • R. Akhil and B.A. Goud, “Delay and Area Analysis of Hardware Implementation of FFT using FPGA”, Proceedings of IEEE International Conference on Electronics, Computing and Communication Technologies, pp. 1-6, 2020


Abstract Views: 315

PDF Views: 0




  • HIGH PERFORMANCE FIR FILTER BASED ON PIPELINED PARALLEL PREFIX ADDER FOR SIGNAL PROCESSING APPLICATIONS

Abstract Views: 315  |  PDF Views: 0

Authors

Basavoju Harish
Department of Electronics and Communication Engineering, Vignan’s Lara Institute of Technology and Science., India
M.S.S. Rukmini
Department of Electronics and Communication Engineering, Vignan’s Foundation for Science, Technology and Research., India
K. Sivani
Department of Electronics and Instrumentation Engineering, Kakatiya Institute of Technology and Science., India

Abstract


Multiple adders and multipliers make up a complex digital signal processing system (DSP). The efficient design of adders and multipliers improves the DSP system performance. In this paper, modified 4-Tap digital Finite Impulse Response (FIR) filter is built using the Pipelined Brent-Kung adder (PBKA) and a Vedic multiplier. The top-level module (FIR filter) is created by writing PBKA and PBKA-based Vedic multiplier Verilog code. The results of Pipelined Brent Kung adderbased FIR filter are compared with BKA and KSA-based 4-Tap digital FIR filter. According to the synthesis results, the PBKA-based FIR filter operates 57% faster than the BKA-based FIR filter. In terms of Power Delay Product (PDP) PBKA based FIR filter is 22% efficient than BKA based FIR filter. Xilinx 14.7 ISE software is used for simulation, while Virtex-7 FPGA is used for synthesis

Keywords


Brent Kung Adder, FIR Filter, Kogge Stone Adder, Parallel Prefix Adder, Pipelined Brent Kung Adder, Vedic Multiplier, Virtex 7 FPGA

References