ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

AN EFFICIENT NOVEL 6T SRAM CELL WITH OPTIMIZED LAYOUT AND DESIGN METRICS IN 45NM TECHNOLOGY


Affiliations
1 Department of Electronics and Communication Engineering, I.K. Gujral Punjab Technical University., India
2 Department of Electronics and Communication Engineering, National Institute of Technical Teachers Training and Research., India
     

   Subscribe/Renew Journal


In this paper, a novel 6T SRAM (Static Random Access Memory) cell is proposed with fast performance, high density, and low power consumption. The proposed configuration has exploited the benefits of feedback cutting transistor for the efficient and stable bit storage and transmission gate transistor for fast and power efficient structure. The proposed structure is comparatively more area efficient due to the use of more PMOS (P-Channel Metal-Oxide Semiconductor) transistors than NMOS (N-Channel Metal-Oxide Semiconductor) transistors without any performance degradation. It has been founded that the proper management of transistor blocks can play an important role in designing an efficient circuit. The presented SRAM cell consumes lesser power, is faster, and is taking relatively less read and write time as compared to standard 6T cell and previous configurations. The data bits in the cell are efficiently stored and are stable. The novel SRAM cell is 24.17% more compact than the traditional 6T SRAM structure. Simulation findings demonstrate that the suggested cell has shown significant improvement in performance characteristics such as reduction in leakage current, power consumption, and delay (range of 8.66% to 77.7%) as compared to similar latest research which includes advanced and costlier technologies like FINFETs (Fin Field-Effect Transistor). The proposed 6T structure is simulated in 45nm technology node using the cadence virtuoso tool.

Keywords

Novel 6T Configuration, Complementary Metal-Oxide Semiconductor SRAM Cell, Low Power SRAM Cell, 45nm Technology Node, SRAM Layout
Subscription Login to verify subscription
User
Notifications
Font Size

  • K. Khare, N. Khare, V. Kumar Kulhade and P. Deshpande, “VLSI Design and Analysis of Low Power 6T SRAM Cell using Cadence Tool”, Proceedings IEEE International Conference on Semiconductor Electronics, pp. 117-121, 2008.

  • B.C. Paul, A. Agarwal and K. Roy, “Low-Power Design Techniques for Scaled Technologies”, Integration, Vol. 39, No. 2, pp. 64-89, 2006.

  • S. Akashe, S. Bhushan and S. Sharma, “High Density and Low Leakage Current based 5T SRAM Cell using 45 nm Technology”, Proceedings International Conference on Nanoscience, Engineering and Technology, pp. 346-350, 2011.

  • P.N. Guo, C.K. Cheng and T. Yoshimura, “An O-Tree Representation of Non-Slicing Floorplan and its Applications”, Proceedings of International Conference on Design Automation, pp. 268-273, 1999.

  • Y.C. Chang, Y.W. Chang, G.M. Wu and S.W. Wu, “B*- Trees: A New Representation for Non-Slicing Floorplans”, Proceedings of International Conference on Design Automation, pp. 458-463, 2000.

  • R. Gupta and S.S. Gill, “Adaptive Memetic Algorithm on Novel CBLSP Algorithm for O-Tree Implementation”, Proceedings of International Conference on Advances in VLSI and Embedded Systems, pp. 1-13, 2021.

  • R.K. Nain and M. Chrzanowska Jeske, “Fast PlacementAware 3-D Floor Planning using Vertical Constraints on Sequence Pairs”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 9, pp. 1667-1680, 2011.

  • V.S. Babu, “Solid State Device and Technology”, Pearson Publication, 2008.

  • N. Rahman and B.P. Singh, “Design of Low Power SRAM Memory using 8T SRAM Cell”, International Journal on Recent Technology and Engineering, Vol. 2, No. 1, pp. 123- 127, 2013. ISSN: 2395-1680 (ONLINE) ICTACT JOURNAL ON MICROELECTRONICS, JULY 2022, VOLUME: 08, ISSUE: 02 1357

  • L. Villa, M. Zhang and K. Asanovic, “Dynamic Zero Compression for Cache Energy Reduction”, Proceedings on Annual IEEE/ACM International Symposium on Microarchitecture, pp. 214-220, 2000.

  • L. Chang, “Stable SRAM Cell Design for the 32 nm Node and Beyond”, Proceedings of Symposium on Digest of Technical Papers on VLSI Technology, pp. 128-129, 2005.

  • S. Mishra, A. Dubey, S.S. Tomar and S. Akashe, “Design and Simulation of High Level Low Power 7T SRAM Cell using Various Process and Circuit Techniques”, Proceedings of IEEE International Conference on Signal Processing, Computing and Control, pp. 1-7, 2012.

  • N.H.E. Weste, D. Harris and A. Banerjee, “CMOS VLSI Design”, Pearson Education, 2005.

  • R. Gupta, S.S. Gill and N. Kaur, “A Novel Low Leakage and High Density 5T CMOS SRAM Cell in 45nm Technology”, Proceedings of International Conference on Recent Advances in Engineering and Computational Sciences, pp. 1-6, 2014.

  • A.A. Kumar and A. Chalil, “Performance Analysis of 6T SRAM Cell on Planar and FinFET Technology”, Proceedings of International Conference on Communication and Signal Processing, pp. 375-379, 2019.

  • S. Akashe, S. Rastogi and S. Sharma, “Specific Power Illustration of Proposed 7T SRAM with 6T SRAM using 45 nm Technology”, Proceedings of International Conference on Nanoscience, Engineering and Technology, pp. 364-369, 2011.

  • V.K. Joshi and S. Borkar, “A Comparative Study of NC and PP-SRAM Cells with 6T SRAM Cell using 45nm CMOS Technology”, Proceedings of International Conference on Advances in Electrical, Electronic and Systems Engineering, pp. 58-62, 2016.

  • A. Bhaskar, “Design and Analysis of Low Power SRAM Cells”, Proceedings of International Conference on Innovations in Power and Advanced Computing Technologies, pp. 1-5, 2017.

  • S. S. R.B. R. S., Samiksha, R. Banu and P. Shubham, “Design and Performance Analysis of 6T SRAM Cell in 22nm CMOS and FINFET Technology Nodes”, Proceedings of International Conference on Recent Advances in Electronics and Communication Technology, pp. 38-42, 2017.

  • J.K. Mishra, H. Srivastava, P.K. Misra and M. Goswami, “A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology”, Proceedings of IEEE International Symposium on Smart Electronic Systems, pp. 1-5, 2018.

  • Y. Sharma, A. Singh and A. Pandey, “Comparative Design and Analysis of FinFET and CMOS SRAM Cell,” in Proceedings 2019 International Conference on Signal Processing and Communication (ICSC), pp. 275-278, 2019.

  • R.R. Vallabhuni, P. Shruthi, G. Kavya and S. Siri Chandana, “6Transistor SRAM Cell Designed using 18nm FinFET Technology”, Proceedings of International Conference on Intelligent Sustainable Systems, pp. 1584-1589, 2020.

  • J. K. Mishra, P. Kumar Misra and M. Goswami, “A Low Power 7T SRAM cell using Supply Feedback Technique at 28nm CMOS Technology”, Proceedings of International Conference on Signal Processing and Integrated Networks, pp. 597-602, 2020.

  • A. Chunn, A. Agrawal and A. Naugarhiya, “An 8T TGDTMOS Based Subthreshold SRAM Cell with Improved Write Ability and Access Times”, Proceedings of International Symposium on VLSI Design and Test, pp. 1-6, 2020.

  • G. Ravikishore. and N.M. Nandhitha, “6T-SRAM Design to Optimize Delay using Finfet Technology”, Proceedings International Conference on Intelligent Communication Technologies and Virtual Mobile Networks, pp. 540-544, 2021.

  • D. Sharma and S. Birla, “Design and Analysis of 10T SRAM Cell with Stability Characterizations”, Proceedings of International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies, pp. 1-5, 2021.

  • J.T. Kao and A.P. Chandrakasan, “Dual-Threshold Voltage Techniques for Low-Power Digital Circuits”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 7, pp. 1009-1018, 2000.

  • B.N.K. Reddy, K. Sarangam, T. Veeraiah and R. Cheruku, “SRAM Cell with Better Read and Write Stability with Minimum Area”, Proceedings IEEE Region 10 Conference, pp. 2164-2167, 2019.

  • T.S. Kumar, S.L. Tripathi and S.K. Sinha, “Comparative Analysis of Leakage Power in 18nm 7T and 8T SRAM cell Implemented with SVL Technique”, Proceedings of International Conference on Intelligent Engineering and Management, pp. 121-124, 2020


Abstract Views: 317

PDF Views: 0




  • AN EFFICIENT NOVEL 6T SRAM CELL WITH OPTIMIZED LAYOUT AND DESIGN METRICS IN 45NM TECHNOLOGY

Abstract Views: 317  |  PDF Views: 0

Authors

Rohin Gupta
Department of Electronics and Communication Engineering, I.K. Gujral Punjab Technical University., India
Sandeep Singh Gill
Department of Electronics and Communication Engineering, National Institute of Technical Teachers Training and Research., India

Abstract


In this paper, a novel 6T SRAM (Static Random Access Memory) cell is proposed with fast performance, high density, and low power consumption. The proposed configuration has exploited the benefits of feedback cutting transistor for the efficient and stable bit storage and transmission gate transistor for fast and power efficient structure. The proposed structure is comparatively more area efficient due to the use of more PMOS (P-Channel Metal-Oxide Semiconductor) transistors than NMOS (N-Channel Metal-Oxide Semiconductor) transistors without any performance degradation. It has been founded that the proper management of transistor blocks can play an important role in designing an efficient circuit. The presented SRAM cell consumes lesser power, is faster, and is taking relatively less read and write time as compared to standard 6T cell and previous configurations. The data bits in the cell are efficiently stored and are stable. The novel SRAM cell is 24.17% more compact than the traditional 6T SRAM structure. Simulation findings demonstrate that the suggested cell has shown significant improvement in performance characteristics such as reduction in leakage current, power consumption, and delay (range of 8.66% to 77.7%) as compared to similar latest research which includes advanced and costlier technologies like FINFETs (Fin Field-Effect Transistor). The proposed 6T structure is simulated in 45nm technology node using the cadence virtuoso tool.

Keywords


Novel 6T Configuration, Complementary Metal-Oxide Semiconductor SRAM Cell, Low Power SRAM Cell, 45nm Technology Node, SRAM Layout

References