ICTACT Journal on Microelectronics

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AN EFFICIENT NOVEL 6T SRAM CELL WITH OPTIMIZED LAYOUT AND DESIGN METRICS IN 45NM TECHNOLOGY


Affiliations
1 Department of Electronics and Communication Engineering, I.K. Gujral Punjab Technical University., India
2 Department of Electronics and Communication Engineering, National Institute of Technical Teachers Training and Research., India
     

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In this paper, a novel 6T SRAM (Static Random Access Memory) cell is proposed with fast performance, high density, and low power consumption. The proposed configuration has exploited the benefits of feedback cutting transistor for the efficient and stable bit storage and transmission gate transistor for fast and power efficient structure. The proposed structure is comparatively more area efficient due to the use of more PMOS (P-Channel Metal-Oxide Semiconductor) transistors than NMOS (N-Channel Metal-Oxide Semiconductor) transistors without any performance degradation. It has been founded that the proper management of transistor blocks can play an important role in designing an efficient circuit. The presented SRAM cell consumes lesser power, is faster, and is taking relatively less read and write time as compared to standard 6T cell and previous configurations. The data bits in the cell are efficiently stored and are stable. The novel SRAM cell is 24.17% more compact than the traditional 6T SRAM structure. Simulation findings demonstrate that the suggested cell has shown significant improvement in performance characteristics such as reduction in leakage current, power consumption, and delay (range of 8.66% to 77.7%) as compared to similar latest research which includes advanced and costlier technologies like FINFETs (Fin Field-Effect Transistor). The proposed 6T structure is simulated in 45nm technology node using the cadence virtuoso tool.

Keywords

Novel 6T Configuration, Complementary Metal-Oxide Semiconductor SRAM Cell, Low Power SRAM Cell, 45nm Technology Node, SRAM Layout
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  • AN EFFICIENT NOVEL 6T SRAM CELL WITH OPTIMIZED LAYOUT AND DESIGN METRICS IN 45NM TECHNOLOGY

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Authors

Rohin Gupta
Department of Electronics and Communication Engineering, I.K. Gujral Punjab Technical University., India
Sandeep Singh Gill
Department of Electronics and Communication Engineering, National Institute of Technical Teachers Training and Research., India

Abstract


In this paper, a novel 6T SRAM (Static Random Access Memory) cell is proposed with fast performance, high density, and low power consumption. The proposed configuration has exploited the benefits of feedback cutting transistor for the efficient and stable bit storage and transmission gate transistor for fast and power efficient structure. The proposed structure is comparatively more area efficient due to the use of more PMOS (P-Channel Metal-Oxide Semiconductor) transistors than NMOS (N-Channel Metal-Oxide Semiconductor) transistors without any performance degradation. It has been founded that the proper management of transistor blocks can play an important role in designing an efficient circuit. The presented SRAM cell consumes lesser power, is faster, and is taking relatively less read and write time as compared to standard 6T cell and previous configurations. The data bits in the cell are efficiently stored and are stable. The novel SRAM cell is 24.17% more compact than the traditional 6T SRAM structure. Simulation findings demonstrate that the suggested cell has shown significant improvement in performance characteristics such as reduction in leakage current, power consumption, and delay (range of 8.66% to 77.7%) as compared to similar latest research which includes advanced and costlier technologies like FINFETs (Fin Field-Effect Transistor). The proposed 6T structure is simulated in 45nm technology node using the cadence virtuoso tool.

Keywords


Novel 6T Configuration, Complementary Metal-Oxide Semiconductor SRAM Cell, Low Power SRAM Cell, 45nm Technology Node, SRAM Layout

References