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Literature Survey On Area Optimization Of Cmos Full Adder Design
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In this paper, a novel architecture for a dynamic logic-based full adder is introduced and analyzed. In full adder architecture, the XOR and XNOR gates are commonly employed as basic logic units. In the report, improved XOR and XNOR logic gate topologies are employed to produce a full adder circuit. The envisioned XOR/XNOR gate architecture has a full logic cycle. The suggested adder design is modelled using a traditional 180 nm CMOS technique. The simulated outcomes using the SPICE simulation tool demonstrated that the proposed network has significant advantages in energy loss and efficiency while compared to previously published designs
Keywords
MOS Current-Mode Logic (MCML), Ternary Full-Adder (TFA), Low Power, Gate-Diffusion-Input (GDI), Ripple Carry Adder (RCA)
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- S. Malipatil, Vikas Maheshwari and Marepally Bhanu Chandra, “Area Optimization of CMOS Full Adder Design Using 3T XOR”, Proceedings of International Conference on Wireless Communication Signal Processing and Networking, pp. 1-7, 2020.
- Aloke Sahaa, Rakesh Kumar Singh, Pragya Gupta and Dipankar Pal, “DPL-Based Novel CMOS 1-Trit Ternary
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- S. Akhter, “An Efficient CMOS Dynamic Logic- Based Full Adder”, Proceedings of International Conference on Signal Processing and Communication, pp. 1-8, 2020.
- Harsh Yadav, Amit Kumar Goyal and Ajay Kumar, “Design Analysis and Comparative Study of GDI Based Full Adder Design”, Proceedings of International Conference on Signal Processing and Communication, pp. 991-998, 2020.
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- M. Hasan, “A Novel Hybrid Full Adder based on Gate Diffusion Input Technique, Transmission Gate and Static CMOS Logic”, Proceedings of International Conference on Gate High Speed Computing, Communication and Networking Technologies, pp. 443-456, 2019.
- K. Murugan and S. Baulkani, “VLSI Implementation of Ultra Power Optimized Adiabatic Logic Based Full Adder Cell”, Microprocessors and Microsystems, Vol. 70, pp. 1520, 2019.
- Khaled Alhaj, “MRL Crossbar-Based Full Adder Design”, Proceedings of IEEE International Conference on Electronics, Circuits and Systems, pp. 154-160, 2019.
- Malti Bansal and Jasmeet Singh, “Qualitative Analysis of CMOS Logic Full Adder and GDI Logic Full Adder using 18 nm FinFET Technology”, Proceedings of International Conference on Recent Developments in Control, Automation and Power Engineering, pp. 330-338, 2019.
- Inamul Hussain and Saurabh Chaudhury, “Performance Comparison of 1-Bit Conventional and Hybrid Full Adder Circuits”, Proceedings of International Conference on Advances in Communication, Devices and Networking, pp.43-50, 2018.
- Muhammad Hussnain, “Low Power 4× 4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder”, Proceedings of International Bhurban Conference on Applied Sciences and Technology, pp. 78-86, 2018.
- Lei Wang and Guangjun Xie, “Novel Designs of Full Adder in Quantum-Dot Cellular Automata Technology”, The Journal of Supercomputing, Vol. 74, pp. 4798-4816, 2018.
- Firdous Ahmad, “Modular Design of Ultra-Efficient Reversible Full Adder-Subtractor in QCA with Power Dissipation Analysis”, International Journal of Theoretical Physics, Vol. 57, pp. 1-16, 2018
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