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Analysis And Implementation Of Mac Unit For Different Precisions
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This paper describes the design of the multiply- Accumulate unit and compares all parameters of the 4-bit, 8-bit, 12-bit, and 16-bit MAC unit. MAC is the basic unit that performs the multiplication operation and addition/accumulation operation. This MAC unit is designed on Vivado HLS software using LUTs at room temperature. These designs are analyzed and simulated by using the Vivado HLS tool and implemented on Zybo Evaluation and Development kit (xc7z020clg400-1).
Keywords
MAC unit, LUTs, Power, Delay, and Utilization
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- G. Raut, S. Rai, S.K. Vishvakarma and A. Kumar, “Recon: Resource Efficient Cordic-Based Neuron Architecture”, IEEE Open Journal of Circuits and Systems, Vol. 2, pp. 170181, 2021.
- A.S.K. Vamsi and S. Ramesh, “An Efficient Design of 16 Bit Mac Unit using Vedic Mathematics”, Proceedings of International Conference on Communication and Signal Processing, pp. 319-322, 2019.
- M. Yuvaraj, B.J. Kailath and N. Bhaskhar, “Design of Optimized Mac Unit using Integrated Vedic Multiplier”, Proceedings of International Conference on Microelectronic Devices, Circuits and Systems, pp. 1-6, 2017.
- S. Langer, “Approximating Smooth Functions by Deep Neural Networks with Sigmoid Activation Function”, Journal of Multivariate Analysis, Vol. 182, pp. 104696104699, 2021.
- J. Ma, R.P. Sheridan, A. Liaw, G.E. Dahl and V. Svetnik, “Deep Neural Nets as a Method for Quantitative StructureActivity Relationships”, Journal of Chemical Information and Modeling, Vol. 55, No. 2, pp. 263-274, 2015.
- K.L. Du and M. Swamy, “Neural Network Circuits and Parallel Implementations”, Neural Networks and Statistical Learning, PP. 829-851, 2019.
- Y. Umuroglu, N.J. Fraser, G. Gambardella, M. Blott, P. Leong, M. Jahre and K. Vissers, “Finn: A Framework for Fast, Scalable Binarized Neural Network Inference”, Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 65-74, 2017.
- K. Simonyan and A. Zisserman, “Very Deep Convolutional Networks for Large-Scale Image Recognition”, Proceedings of International Conference on Microelectronic Devices, pp. 1-6, 2014.
- A. Bifet and E. Frank, “Sentiment Knowledge Discovery in Twitter Streaming Data”, Proceedings of International Conference on Discovery Science, pp. 1-15, 2010.
- E. Nurvitadhi, D. Sheffield, J. Sim, A. Mishra, G. Venkatesh and D. Marr, “Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC”, Proceedings of International Conference on Field-Programmable Technology, pp. 77-84, 2016.
- I. Kuon and J. Rose, “Measuring the Gap between FPGAs and ASICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 2, pp. 203215, 2007.
- F. Kastner, B. Janben, F. Kautz, M. Hubner and G. Corradi, “Hardware/Software Codesign for Convolutional Neural Networks Exploiting Dynamic Partial Reconfiguration on PYNQ”, Proceedings of IEEE International Symposium Workshops on Parallel and Distributed Processing, pp. 154161, 2018.
- E. Wu, X. Zhang, D. Berman, I. Cho and J. Thendean, “Compute Efficient Neural-Network Acceleration”, Proceedings of International Symposium on FieldProgrammable Gate Arrays, pp. 191-200, 2019.
- A. Apicella, F. Donnarumma, F. Isgro and R. Prevete, “A Survey on Modern Trainable Activation Functions”, Neural Networks, Vol. 13, No. 2, pp. 1-17, 2021.
- W. Yan, M.D. Ercegovac and H. Chen, “An EnergyEfficient Multiplier with Fully Overlapped Partial Products Reduction and Final Addition”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 63, No. 11, pp. 1954-1963, 2016.
- S.M. Antony, S.S.R. Prasanthi, S. Indu and R. Pandey, “Design of High-Speed Vedic Multiplier using Multiplexer Based Adder”, Proceedings of International Conference on Control Communication and Computing, pp. 448-453, 2015.
- M.U. Maheswara Sainath and B. Sekhar, “High Speed Vedic Multiplier”, International Journal of Engineering Research, Vol. 2, No. 3, pp. 1-15, 2014.
- L. Ciminiera and A. Valenzano, “Low Cost Serial Multipliers for High Speed Specialised Processors”, IEE Proceedings E (Computers and Digital Techniques), Vol. 135, No. 5, pp. 259-265, 1988
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