https://i-scholar.in/index.php/IJMicroE/issue/feed ICTACT Journal on Microelectronics 2022-09-07T06:32:36+00:00 Editor raghav@ictact.in Open Journal Systems ICTACT Journal on Microelectronics (IJME) is a peer-reviewed International Journal published quarterly. IJME welcomes Scientists, Research Scholars, Academicians, Engineers to submit their original research papers which is neither published nor currently under review by other journals or conferences. Papers should emphasize original results relating to various aspects of Microelectronics. Review articles, focusing on multidisciplinary views of Micro-electronics are also welcome. The Journal will address the continued growth, concerns &amp; challenges encountered, solutions adopted in the field of Microelectronics. https://i-scholar.in/index.php/IJMicroE/article/view/214811 CPW FED ULTRA COMPACT RADIATOR FOR 2.4 GHZ WIRELESS AND ISM APPLICATIONS 2022-09-07T06:32:35+00:00 Sreejith M. Nair Manju Abraham S. Sindhu <strong><em>A Uniplanar CPW fed electrically small radiator suitable for WiFi 802.11b, 802.11g, 802.11n, Bluetooth, ZigBee IEEE802.15.4 and ISM application is developed and presented. Physical structure of the developed antenna is very compact of the order of 0.12λg × 0.10λg × 0.02λg which makes it very suitable for almost all the 2.4GHz based wireless applications. Parametric studies of the antenna is performed and from the results obtained design equations of the structure is developed and verified. Computational model of the antenna is also developed using FDTD and the results are compared and discussed. Antenna offers uniform radiation characteristics with good radiation efficiency and gain.</em></strong> 2022-07-31T00:00:00+00:00 https://i-scholar.in/index.php/IJMicroE/article/view/214823 DESIGN OF TWO STAGE CMOS OPERATIONAL AMPLIFIER IN 180NM TECHNOLOGY WITH LOW POWER, HIGH GAIN AND HIGH SWING 2022-09-07T06:32:36+00:00 Durgesh Pratap Nishant Singh Shiksha Jain <em><strong>For certain applications, high bandwidth operational amplifiers are required. This necessitates research into the area of op-amp bandwidth expansion without influencing any other parameters significantly. This study presents a CMOS two-stage 0perational amplifier, that operates at 1.8 V power supply in 180 nm technology and has a bias current dependent input terminal. The supply voltage has been reduced to lower the system’s overall power usage. Our primary goal is to reduce power loss, higher gain, and higher difference between maximum voltage and minimum voltage at output port. There is a trade-off between rate, power, and benefit at high supply voltages. The rate, power, and benefit of any circuit determine its performance. This op-amp has low standby power expenditure, with high driving capability, and runs at low voltage, consequential a low-power circuit. The op-amp has a gain of 70.37 decibel, a bandwidth of 53.01 MHz, and a phase margin of 27.83 degree. The operational amplifier power consumption and CMRR are also determined as 523µW and 73.33 decibel, respectively.</strong></em> 2022-07-31T00:00:00+00:00 https://i-scholar.in/index.php/IJMicroE/article/view/214828 HIGH PERFORMANCE FIR FILTER BASED ON PIPELINED PARALLEL PREFIX ADDER FOR SIGNAL PROCESSING APPLICATIONS 2022-09-07T06:32:36+00:00 Basavoju Harish M.S.S. Rukmini K. Sivani <em><strong>Multiple adders and multipliers make up a complex digital signal processing system (DSP). The efficient design of adders and multipliers improves the DSP system performance. In this paper, modified 4-Tap digital Finite Impulse Response (FIR) filter is built using the Pipelined Brent-Kung adder (PBKA) and a Vedic multiplier. The top-level module (FIR filter) is created by writing PBKA and PBKA-based Vedic multiplier Verilog code. The results of Pipelined Brent Kung adderbased FIR filter are compared with BKA and KSA-based 4-Tap digital FIR filter. According to the synthesis results, the PBKA-based FIR filter operates 57% faster than the BKA-based FIR filter. In terms of Power Delay Product (PDP) PBKA based FIR filter is 22% efficient than BKA based FIR filter. Xilinx 14.7 ISE software is used for simulation, while Virtex-7 FPGA is used for synthesis</strong></em> 2022-07-31T00:00:00+00:00 https://i-scholar.in/index.php/IJMicroE/article/view/214831 ELIMINATE THE INTERFERENCE IN 5G ULTRA-WIDE BAND COMMUNICATION ANTENNAS IN CLOUD COMPUTING NETWORKS 2022-09-07T06:32:36+00:00 G. Ramesh J. Logeshwaran V. Aravindarajan Feny Thachil <em>In this era of technology, every day we see a new change in new development. It is truly astonishing the impressive speed we are seeing, especially in communication technology. This is where 5G comes into play. Transmission stations carry a small amount of transmitted coded signal. Especially when setting up antennas, use them. However, classical versions are based on inductive communication via a measured oscillating circuit. In most cases their small impulses do not allow sufficient contact with antenna elements, for example, with a wire frame. As a result, the indication of the frequency of the element becomes unclear, which leads to significant measurement errors. In this paper, a smart construction of 5G ultra-wide band communication antennas is designed to eliminate the interferences in cloud computing networks. The proposed design simply solved this problem by making a simple special girder to construct its “double square” elements. In a cut-off signal level, the proposed UWBCA design achieved 97.70% of peak data rate, 96.61% of antenna latency, 94.81% of antenna capacity, 96.33% of spectral efficiency and 94.99% of connection density. This proposed design increases its constructive efficiency and contact area from the classic types and prevents interference.</em> 2022-07-31T00:00:00+00:00 https://i-scholar.in/index.php/IJMicroE/article/view/214833 DESIGN OF NOISE TOLERANCE 9T SRAM CELL 2022-09-07T06:32:36+00:00 Chandramuleswar Roy Naveen Jaswanth Achari Naresh K. Reddy <strong><em>This paper describes the well-thought-out design of a 9T Static Random Access Memory single Bit cell with enhanced performance. MonteCarlo simulations are utilized for this proposed 9T SRAM circuit, and the outcomes are verified by comparing with various like Conv6T, Conv7T and Conv8T SRAM cells in the 22-nm PTM with variable supply voltage. The proposed 9T SRAM shows 1.02/1.265/ 0.259 × lesser read delay and 1.028/1.032/0.857 × write delay as compared to Conv6T/Conv7T/ Conv8T respectively. Our proposed 9T SRAM showing 2.06/12.5 × less leakage power dissipation as compared to Conv6T/ Conv8T respectively.</em></strong> 2022-07-31T00:00:00+00:00 https://i-scholar.in/index.php/IJMicroE/article/view/214836 AN EFFICIENT NOVEL 6T SRAM CELL WITH OPTIMIZED LAYOUT AND DESIGN METRICS IN 45NM TECHNOLOGY 2022-09-07T06:32:36+00:00 Rohin Gupta Sandeep Singh Gill <em>In this paper, a novel 6T <strong>SRAM</strong> <strong>(Static Random Access Memory)</strong> cell is proposed with fast performance, high density, and low power consumption. The proposed configuration has exploited the benefits of feedback cutting transistor for the efficient and stable bit storage and transmission gate transistor for fast and power efficient structure. The proposed structure is comparatively more area efficient due to the use of more<strong> PMOS</strong> <strong>(P-Channel Metal-Oxide Semiconductor)</strong> transistors than <strong>NMOS</strong> <strong>(N-Channel Metal-Oxide Semiconductor)</strong> transistors without any performance degradation. It has been founded that the proper management of transistor blocks can play an important role in designing an efficient circuit. The presented<strong> SRAM</strong> cell consumes lesser power, is faster, and is taking relatively less read and write time as compared to standard 6T cell and previous configurations. The data bits in the cell are efficiently stored and are stable. The novel<strong> SRAM</strong> cell is 24.17% more compact than the traditional 6T <strong>SRAM</strong> structure. Simulation findings demonstrate that the suggested cell has shown significant improvement in performance characteristics such as reduction in leakage current, power consumption, and delay (range of 8.66% to 77.7%) as compared to similar latest research which includes advanced and costlier technologies like <strong>FINFETs</strong> <strong>(Fin Field-Effect Transistor)</strong>. The proposed 6T structure is simulated in 45nm technology node using the cadence virtuoso tool.</em> 2022-07-31T00:00:00+00:00 https://i-scholar.in/index.php/IJMicroE/article/view/214838 PULSE WIDTH MODULATOR USING OTRA BASED TIMER CIRCUIT 2022-09-07T06:32:36+00:00 Dheeraj Singh Rajput Ritu Gupta Sankalp Shukla Deep Kishore Parsediya <em>This paper proposes a modified <strong>PWM</strong> circuit using <strong>OTRA</strong> based analog timer circuit. Designing a pulse width modulator circuit by employing the proposed analog timer circuit results in a waveform having variable duty cycle and time period. The timer circuit consists of comparators designed using <strong>OTRA</strong> and flip flops. The fabrication of timer circuit on a monolithic integrated circuit is easier as the carrier signal type is exponential and no additional circuitry is needed unlike for triangular and sawtooth pulses. The process parameters of 0.5 µm <strong>CMOS</strong> have been used for performing an intensive simulation of the proposed PWM circuit.</em> 2022-07-31T00:00:00+00:00 https://i-scholar.in/index.php/IJMicroE/article/view/214839 AN EFFECTIVE MEASUREMENT OF HIGH SPEED COMMUNICATION NETWORK ANTENNA DESIGN IN 5G BROADBAND APPLICATION 2022-09-07T06:32:36+00:00 A. Vaniprabha R. Prakash T. Kiruthiga <em>An access point is a wireless base station designed to provide wireless access to an existing network (wireless or wired) or to create an entirely new wireless network. Wireless communication is done through <strong>5G</strong> broadband antenna design technology. Drawing an analogy, the access point can be conditionally compared to the tower of a cellular operator, the access point has a short range and the connection between the devices connected to it is carried out using<strong> 5G</strong> broadband antenna design technology. The range of a standard access point is approximately 200-250 meters, provided there are no obstacles at this distance. In most cases, wireless networks (using access points and routers) are built commercially to attract revenue from customers and tenants. In this paper the designing of high-speed communication network antenna for <strong>5G</strong> broadband applications. This proposed <strong>5G</strong> broadband antenna design acquirers have experience in preparing and implementing the following plans for implementing network infrastructure based on wireless solutions. It should be noted that the <strong>SSID</strong> (Wireless Network Identifier), Channel and Encryption Type must match for correct operation in Repeater and Bridge modes.</em> 2022-07-31T00:00:00+00:00 https://i-scholar.in/index.php/IJMicroE/article/view/214840 100MHZ-2GHZ PULSE TRIGGERED FLIP-FLOPS IN 32NM TECHNOLOGY FOR LOW POWER AND HIGH PERFORMANCE DIGITAL CMOS CIRCUITS 2022-09-07T06:32:36+00:00 Owais Ahmad Shah Geeta Nijhawan Imran Ahmed Khan <em>This study presents extensive work carried out on pulse triggered flip flops <strong>(P-FFs)</strong> for power consumption, area requirements and delay measurements. Six latest state-of-art P-FFs are used to determine these performance parameters. The flip flops are Conditional Pulse Enhancement<strong> P</strong>-<strong>FF (CPEPFF),</strong> Signal Feed-through<strong> P-FF (SFTPFF)</strong> Karimi’s<strong> P-FF (KPFF),</strong> Conditional Feed-through P-<strong>FF (CFTPFF)</strong>, Dual Dynamic node hybrid <strong>FF (DDFF)</strong>, and Dual-edge Implicit FF with an embedded Clock Gated Scheme <strong>(DIFF-CGS)</strong>. Simulations are carried out at 32nm <strong>CMOS</strong> technology on T-SPICE at operating conditions of 500MHz clock frequency, temperature of 25°C with 50% data activity. Results showed that <strong>CFTPFF</strong> consumes the least average power with minimum reduction of 27.94% and maximum of 57.45%. Even at higher frequencies and varying data activities CFTPFF outperforms other FFs in power dissipation. <strong>DDFF</strong> is the fastest <strong>P-FF</strong> with minimum enhancements of 82.7% and maximum 94%. In terms of power delay product (PDP), the optimal PDP of <strong>DDFF</strong> is best among all the P-FFs whereas<strong> DIFF-CGS</strong> has the worst. The area overhead of <strong>KPFF</strong> and <strong>CFTPFF</strong> is better compared to the rest of<strong> P-FFs</strong>.</em> 2022-07-31T00:00:00+00:00