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Aravindhan, A.
- Case Study of Explicit and Implicit Pulsed Flip Flops with Conditional Pulse Enhancement Mechanism
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1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
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ICTACT Journal on Microelectronics, Vol 1, No 3 (2015), Pagination: 120-123Abstract
In this paper a study of power efficient pulse triggered flip flops was conducted by adopting a pulse control scheme (PCS), named conditional pulse enhancement. The conditional pulse enhancement scheme consists of a simple pass transistor 'AND' gate design and a pull up 'pMOS'. This set up reduces circuit complexity and removes the pulse generation control logic from the critical path, which facilitate a faster discharge operation as well as improvise the discharge speed conditionally. In this project, the effect of conditional pulse enhancement scheme on the power as well as performance of conventional flip flop such as ep-DCO, ep-CDFF, ip-DCO, are analyzed. The performance analysis was carried out by adopting 180nm CMOS technology. The simulation results reveal that implicit flip flops with conditional pulse enhancement scheme outperforms the conventional flip flops in terms of power and timing characteristics.Keywords
Pulse Triggered Flip Flop (P-FF), Pulse Control Scheme (PCS), Pulse Enhancement, Pass Transistor AND, Pulse Generation.References
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- P. Zhao, T. Darwish and M. Bayoumi, “High-Performance and Low Power Conditional Discharge Flip-Flop”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 5, pp. 477-484, 2004.
- Y.T. Hwang, J.-F. Lin and M.-H. Sheu, “Low Power Pulse Triggered Flip-Flop Design with Conditional Pulse Enhancement Scheme”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 2, pp. 361-366, 2012.
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- Design of Five Port Priority Based Router with Port Selection Logic for NoC
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
2 Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
2 Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, IN
Source
ICTACT Journal on Microelectronics, Vol 2, No 4 (2017), Pagination: 293-299Abstract
Network-on-chip (NoC) is a relatively new technology to signaling that enables not only more efficient interconnects but also more efficient design and verification processes for modern SoCs. The communication through the NoC is performed by enabling processing element (PE) to send and receive packets through the network fabric composed of switches/routers connected together through physical links or channels. For effective global on-chip communication, routers provide efficient routing with comparatively low complexity and high performance. Communication deadlock may appear at the router network and can cause performance degradation and system failure. Based on these studies, a five port priority based router is proposed. Port selection logic is used for selecting the ports for data transmission to selective ports. The proposed router shows better performance when tested in Mesh and Torus topology. Round Robin Algorithm is used in arbiter, which handles the process with priority and has low power consumption. The designed router is implemented in Artix 7, Spartan 6 and Virtex 7 using Xilinx ISE 14.7 design tool and power consumption of five port router is taken in Synopsis VHDL and power compiler tool.Keywords
Network-On-Chip, Router, Communication Deadlock, Port Selection Logic, Round Robin Algorithm.References
- Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris and Axel Jantsch. “Designing 2D and 3D Network-on-chip Architectures”, Springer, 2014.
- William J Dally and Brian Towles, “Route Packets, not Wires: On-Chip Interconnection Networks”, Proceedings of Design Automation Conference, pp. 684-690, 2001.
- Masoud Daneshtalab, “Exploring Adaptive Implementation of On-Chip Networks”, Ph.D Dissertation, Department of Information Technology, University of Turku, 2011.
- Tobias Bjerregaard, and Shankar Mahadevan. “A Survey of Research and Practices of Network-on-Chip”, ACM Computing Surveys, Vol. 38, No. 1, pp. 1-51, 2006.
- Luca Benini and Giovanni De Micheli, “Networks on Chips: A New Paradigm for Systems on Chip Design”, Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 1-2, 2002.
- S. Swapna, Ayas Kanta Swain and Kamala Kanta Mahapatra, “Design and Analysis of Five Port Router for Network on Chip”, Proceedings of IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, pp. 51-54, 2012.
- Maurizio Palesi and Masoud Daneshtalab, “Routing Algorithms in Networks-on- Chip”, Springer, 2014.
- T.A. Bartic, J.Y. Mignolet, Vincent Nollet, Theodore Marescaux, Diederik Verkest, Serge Vernalde and Rudy Lauwereins, “Topology Adaptive Network-on-Chip Design and Implementation”, IEEE Proceedings-Computers and Digital Techniques, Vol. 152, No. 4, pp. 467-472, 2005.
- Wen-Chung Tsai, Ying-Cherng Lan, Yu-Hen Hu and Sao-Jie Chen, “Networks on Chips: Structure and Design Methodologies”, Journal of Electrical and Computer Engineering - Special Issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies, Vol. 2, No. 2, pp. 1-16, 2012.
- Aline Vieira de Mello, Luciano Copello Ost, Fernando Gehm Moraes and Ney Laert Vilar Calazans. “Evaluation of Routing Algorithms on Mesh Based NoCs”, Technical Report Series, Faculdade de Informatica, pp. 1-11, 2004.
- Suyog K Dahule and M. A. Gaikwad, “Design and Simulation of Round Robin Arbiter for NoC Architecture”, International Journal of Engineering and Advanced Technology, pp. 2249-8958, 2012.
- Yanhua Liu, Jie Jin and Zongsheng Lai, “A Dynamic Adaptive arbiter for Network-on-Chip”, Journal of Microelectronics, Electronic Components and Materials, Vol. 43, No. 2, pp. 111-118, 2013.
- Ville Rantala, Teijo Lehtonen and Juha Plosila, “Network on Chip Routing Algorithms”, Available at: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.120.8910&rep=rep1&type=pdf.
- Rickard Holsmark, Maurizio Palesi and Shashi Kumar, “Deadlock Free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions”, Journal of Systems Architecture, Vol. 54, No. 3-4, pp. 427-440, 2008.
- Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny, Michael Shabun and Nir Shmuel, “Heterogeneous NoC Router Architecture”, IEEE Transactions on Parallel and Distributed Systems, Vol. 26, No. 9, pp. 2479-2492, 2015.
- A Case Study on Cluster Based Power-Aware Mapping Strategy for 2D NoC
Abstract Views :311 |
PDF Views:1
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
2 Department of Electronics and Communicaiton Engineering, National Institute of Technology, Tiruchirappalli, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
2 Department of Electronics and Communicaiton Engineering, National Institute of Technology, Tiruchirappalli, IN
Source
ICTACT Journal on Microelectronics, Vol 2, No 4 (2017), Pagination: 315-322Abstract
Network on Chip (NoC) is a growing and prominent paradigm which improves the power and performance of the System on Chip (SoC). Application mapping is one of the major challenges in NoC which maps the various Intellectual Property (IP) cores to standard network topology. Among the various application mapping methods, Integer Linear programming (ILP) is one of the static mapping methods, which finds optimum communication cost. However, it consumes longer computation time. To overcome this limitation, cluster based mapping using KL algorithm has been introduced and it acts poorly at partitioning cut degree. Based on these studies, we propose Fidducia-Mattheyses (FM) algorithm for multi clustering to optimize power consumption and communication cost for different benchmarks of NoC. The effectiveness of the proposed method is verified through VOPD, MPEG 4 and PIP benchmarks. Experimental results show a 4.4% and 34% improvement on communication cost and power consumption respectively for FM algorithm with MPEG 4. However, for VOPD the communication cost and total power consumption is improved with 27% and 35% respectively. On the other hand, PIP benchmark offers identical results in total power consumed and communication cost minimization with existing methods.Keywords
Application Mapping, Integer Linear Programming (ILP), Cluster Based Mapping, Fidducia-Mattheyses (FM) Algorithm.References
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- Radu Marculescu et.al., “Outstanding Research Problems in NoC Design: System, Micro Architecture, and Circuit Perspectives”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 2009, pp. 3-21, 2009.
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- Suleyman Tosun, “New Heuristic Algorithms for Energy Aware Application Mapping and Routing on Mesh-based NoCs”, Systems Architecture, Vol. 57, No. 1, pp. 69-78, 2011.
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