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Chinavenkateswararao, G.
- Design and Implementation of Cache Memory using CMOS Transistors
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, Gudlavalleru Engineering College, IN
1 Department of Electronics and Communication Engineering, Gudlavalleru Engineering College, IN
Source
ICTACT Journal on Microelectronics, Vol 4, No 2 (2018), Pagination: 576-583Abstract
Cache systems are on-chip memory component utilized to store information. Cache serves as a buffer between a CPU and its principle memory. Cache memory is utilized to synchronize the data transfer rate between CPU and principle memory. As cache memory closer to the smaller scale processor, it is faster than the Random access memory (RAM) and principle memory. The advantage of storing data on cache, as compared to RAM, is that it has faster retrieval times, but it has disadvantage of on-chip energy consumption. In term of detecting number of cache hits and miss rate for the range of instructions and less power consumption, the efficient cache memory will be proposed using CMOS transistors. Evaluate the performance of cache memory in terms of power dissipation and speed of operations. Design architect IC, a tool of mentor graphics, is used for designing schematic diagram and eldonet is used for simulation of designed model.Keywords
Cache Memory, Gates, Flip Flops, Register Index, Tag and Power.
References
- John L Henessey and David A Petterson, “Computer Architecture: A Qualitative Approach”, 5th Edition, Morgan Kaufmann, 2011.
- J.H. Chang, H. Chao and Kimming So, “Cache Design of a Sub-Micron CMOS System/370”, Proceedings of 14th Annual International Symposium on Computer Architecture, pp. 208-213, 1987.
- Jongsok Choi, Kevin Nam, Andrew Canis, Jason Anderson, Stephen Brown and Tomasz Czajkowski, “Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems”, Proceedings of IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, pp. 241-248, 2012.
- John P. Hayes, “Computer Architecture and Organization”, Mc Graw Hill, 1988.
- N.P. Jouppi, “Cache Write Policies and Performance”, Proceedings of 20th Annual International Symposium on Computer Architecture, pp. 1911-1920, 1993.
- A. Milenkovic, M. Milenkovic and N. Barnes, “A Performance Evaluation of Memory Hierarchy in Embedded Systems”, Proceedings of 35th Southeastern Symposium System Theory, pp. 427-431. 2003.
- T.S. Warrier, B. Anupama and M. Mutyam, “An Application-Aware Cache Replacement Policy for Last-Level Caches”, Proceedings of International Conference on Architecture of Computing Systems, pp. 207-219, 2013.
- Jianwei Dai and L. Wang, “An Energy-Efficient L2 Cache Architecture using Way Tag Information under Write-Through Policy”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 21, No. 1, pp. 102-112, 2012.
- J. Hong, J. Kim and S. Kim “Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 2, pp. 1-7, 2014.
- Vipin S. Bhure and Praveen R. Chakole, “Design of Cache Controller for Multi-core Processor System”, International Journal of Electronics and Computer Science Engineering, Vol. 1, No. 2, pp. 520-527, 2013.
- H. Noguchi et al., “Highly Reliable and Low-Power Nonvolatile Cache Memory with Advanced Perpendicular STT-MRAM for High Performance CPU”, Proceedings of Symposium on VLSI Circuits Digest of Technical Papers, pp. 1-2, 2014.