International Journal of Research in Signal Processing, Computing & Communication System Design

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Verification of GPIO Core Functions using Universal Verification Methodology


Affiliations
1 Malla Reddy Engineering College for Women, Hyderabad, Telangana State, India
2 Gitam Institute of Technology, Gitam University, Visakhapatnam, AP, India
     

   Subscribe/Renew Journal


The OPB GPIO design provides a general purpose input/output interface to a 32-bit On-Chip Peripheral Bus (OPB). The GPIO IP core is user-programmable generalpurpose I/O controller. That is use is to implement functions that are not implemented with the dedicated controllers in a system and require simple input and/or output software controlled signals. It is one of the important peripheral that is listed on any FPGA board. In this project we are atomizing the operation of the GPIO by writing the code in SYSTEM-VERILOG and simulating it in QUESTA MODELSIM. The main aim of this project is to verify the output by using GPIO pins depending up on the preference the code. We verify the GPIO modules by using UVM [Universal verification Methodology]. The functional verification of the RTL design of the GPIO is carried out for the better optimum design.
User
Subscription Login to verify subscription
Notifications
Font Size

Abstract Views: 289

PDF Views: 1




  • Verification of GPIO Core Functions using Universal Verification Methodology

Abstract Views: 289  |  PDF Views: 1

Authors

K. Niranjan Reddy
Malla Reddy Engineering College for Women, Hyderabad, Telangana State, India
U. DhanaLakshmi
Malla Reddy Engineering College for Women, Hyderabad, Telangana State, India
P. V. Y. Jaya Sree
Gitam Institute of Technology, Gitam University, Visakhapatnam, AP, India

Abstract


The OPB GPIO design provides a general purpose input/output interface to a 32-bit On-Chip Peripheral Bus (OPB). The GPIO IP core is user-programmable generalpurpose I/O controller. That is use is to implement functions that are not implemented with the dedicated controllers in a system and require simple input and/or output software controlled signals. It is one of the important peripheral that is listed on any FPGA board. In this project we are atomizing the operation of the GPIO by writing the code in SYSTEM-VERILOG and simulating it in QUESTA MODELSIM. The main aim of this project is to verify the output by using GPIO pins depending up on the preference the code. We verify the GPIO modules by using UVM [Universal verification Methodology]. The functional verification of the RTL design of the GPIO is carried out for the better optimum design.