International Journal of Scientific Engineering and Technology

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Superiority of Current mode over Voltage mode Interconnects


Affiliations
1 Department of Electronics & Communication Engineering, National Institute of Technology, Hamirpur-177 005, Himachal Pradesh, India
 

In deep submicron VLSI circuits, interconnect delays dominate MOSFET gate delays. Conventional buffer insertion method reduces delays at the cost of valuable chip area. Consequently, alternative methods are essential. Current mode interconnects have lesser delay than voltage mode circuits and also consume lesser chip area. In the present work, superiority of current mode over voltage mode interconnects is analyzed. The simulative analysis is carried out using Tanner EDA tools.
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  • Superiority of Current mode over Voltage mode Interconnects

Abstract Views: 147  |  PDF Views: 0

Authors

Yash Agrawal
Department of Electronics & Communication Engineering, National Institute of Technology, Hamirpur-177 005, Himachal Pradesh, India
Rohit Dhiman
Department of Electronics & Communication Engineering, National Institute of Technology, Hamirpur-177 005, Himachal Pradesh, India
Rajeevan Chandel
Department of Electronics & Communication Engineering, National Institute of Technology, Hamirpur-177 005, Himachal Pradesh, India

Abstract


In deep submicron VLSI circuits, interconnect delays dominate MOSFET gate delays. Conventional buffer insertion method reduces delays at the cost of valuable chip area. Consequently, alternative methods are essential. Current mode interconnects have lesser delay than voltage mode circuits and also consume lesser chip area. In the present work, superiority of current mode over voltage mode interconnects is analyzed. The simulative analysis is carried out using Tanner EDA tools.