Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

ESD Failure Analysis of FPGA and CPLD IC


Affiliations
1 BNM Institute of Technology, Bangalore, India
2 UVCE, Bangalore, India
3 EMI/EMC group, LRDE, Bangalore, India
     

   Subscribe/Renew Journal


Complex electronics devices are becoming more sensitive to electrostatic discharge (ESD). These components are being developed with higher density (extra memory bits per unit volume) and are becoming faster (MHz, GHz, THz, etc.). Indirect and direct air/contact discharge test has been conducted on the ALS-SDA-CPLD/FPGA trainer kit connected to the digital to analog converter (DAC) module. The Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD) are found to be very ESD sensitive. The FPGA 3s50 IC was affected during the contact discharge to input pin. There was damage to the I/O pin bond pad as well as the metal top layer. There was dielectric breakdown damage observed in the CPLD 9572 IC.

Keywords

System Level ESD, FPGA, CPLD, Complex Electronics, Indirect Discharge, Direct Discharge.
User
Subscription Login to verify subscription
Notifications
Font Size

Abstract Views: 169

PDF Views: 0




  • ESD Failure Analysis of FPGA and CPLD IC

Abstract Views: 169  |  PDF Views: 0

Authors

Rajashree Narendra
BNM Institute of Technology, Bangalore, India
M. L. Sudheer
UVCE, Bangalore, India
D. C. Pande
EMI/EMC group, LRDE, Bangalore, India

Abstract


Complex electronics devices are becoming more sensitive to electrostatic discharge (ESD). These components are being developed with higher density (extra memory bits per unit volume) and are becoming faster (MHz, GHz, THz, etc.). Indirect and direct air/contact discharge test has been conducted on the ALS-SDA-CPLD/FPGA trainer kit connected to the digital to analog converter (DAC) module. The Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD) are found to be very ESD sensitive. The FPGA 3s50 IC was affected during the contact discharge to input pin. There was damage to the I/O pin bond pad as well as the metal top layer. There was dielectric breakdown damage observed in the CPLD 9572 IC.

Keywords


System Level ESD, FPGA, CPLD, Complex Electronics, Indirect Discharge, Direct Discharge.