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Design of a Gray Encoder and Counter Using D-FFs and MUXs


Affiliations
1 Department of Electrical and Computer Engineering, College of Engineering, Sultan Qaboos University, Oman
2 Department of Communications and Computers, Helwan University, Egypt
 

This paper proposes a novel design for Binary to Gray code encoders and/or counters using multiplexers and flip-flops. The proposed design are modular based, whereby other stages can be added as per the requirement of the desired applications. Moreover, the external clock timing signal drives only the first stage, while all remaining stages are linked to the outputs from preceding stages. The successive stages transitions at half the rate of the preceding stage thereby, makes the design power efficient since the dissipated power is quadratic frequency dependent. The proposed design can be modified to increase the counters duration or increase the counters resolution according to the applications need. Increasing the Gray counters time span by powers of two simply necessitates augmenting the design by more stages, while maintaining a constant clock rate. On the other hand, doubling the time resolution of the Gray counter over a constant time span can be achieved by adding another stage while subsequently doubling the clock rate.

Keywords

Gray Code, Reflected Binary Code, Encoder, Counter, D-FF.
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  • Design of a Gray Encoder and Counter Using D-FFs and MUXs

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Authors

Al-Busaidi Sayyid Samir
Department of Electrical and Computer Engineering, College of Engineering, Sultan Qaboos University, Oman
Afaq Ahmad
Department of Electrical and Computer Engineering, College of Engineering, Sultan Qaboos University, Oman
Medhat Awadalla
Department of Communications and Computers, Helwan University, Egypt

Abstract


This paper proposes a novel design for Binary to Gray code encoders and/or counters using multiplexers and flip-flops. The proposed design are modular based, whereby other stages can be added as per the requirement of the desired applications. Moreover, the external clock timing signal drives only the first stage, while all remaining stages are linked to the outputs from preceding stages. The successive stages transitions at half the rate of the preceding stage thereby, makes the design power efficient since the dissipated power is quadratic frequency dependent. The proposed design can be modified to increase the counters duration or increase the counters resolution according to the applications need. Increasing the Gray counters time span by powers of two simply necessitates augmenting the design by more stages, while maintaining a constant clock rate. On the other hand, doubling the time resolution of the Gray counter over a constant time span can be achieved by adding another stage while subsequently doubling the clock rate.

Keywords


Gray Code, Reflected Binary Code, Encoder, Counter, D-FF.

References





DOI: https://doi.org/10.13005/ojcst%2F10.03.01