A Low Power 16 Bit Vedic Divider for High Speed VLSI Applications

This paper proposes the implementation of a low power and high speed Vedic Divider based on ancient Indian Vedic mathematics. In this paper, an algorithm based on the "ParavartyaYojayet" is applied, throughout this sutra the propagation delay and power consumption are reduced to an extent. As considered, division operation is more complex in the computation of the digital applications. The most significant aspect of thispaper is to reducethe power consumption and provide high speed. In this work decimal and binary number division algorithms are performed. Synthesis results are calculated on Tanner EDA Tool 13.0 at 32nm technology. The simulated results for proposedVedic divider shows a reduction in delay and power consumption against other division methods.