Design of Power Aware 64 Bit Carry Select Adder for Low Power Arithmetic Circuits at 32nm Technology

As the technology is shrinking day by day, energy and leakage power becoming a critical parameter for modern VLSI design. To full fill the demand and challenge of customer industry is demanding circuits with low power and high performance. In this paper, we have designed 64-bit modified carry select adder by using 6T MUX, 3TAND, 3T XOR and 5Thalf adder configurations which has better performance parameter as compared to the existing design in the literature. To evaluate the performance of modified architecture of carry select adder, extensive simulations are performed by using different bit pattern in T-spice. Result shows that 16-bit carry select adder having improvement in delay upto 34% and average power improves upto 91% and power delay product 92%. The design is extended up to 64bit Carry Select Adder. Results show that by modified Carry select adderconsume lesser average power and power delay product.