High Speed 16-Bit Vedic Multiplier Using Modified Carry Select Adder

In this paper, a low power and high speed 16x16 Vedic Multiplier is designed using modified carry select adder. Modified Carry Select Adder employs a multiplexer and XOR gate based circuit on the intermediate stages instead of BEC and multiplexer which gives low power and high speed of operation. Vedic multiplier is based on the sutra "Urdhva-Tiryakbhyam" (Vertically and crosswise). It is one of the sutras of Vedic mathematics for multiplication. This sutra used both for decimal multiplication and binary multiplication. In this paper, the main goal is to optimize power and speed of multiplier. Simulation result shows that the proposed architecture achieves advantages in terms of PDP (Power delay product) and latency. The latency count improves as compared to the Dadda multiplier. All the Simulations are carried out in H-Spice at 32nm process technology.