HDL Design and Verification of General Purpose Input Output (GPIO) Coprocessor

One of the key features of a microprocessor is to interact with and control peripheral devices. These input/output interfaces may be DMA, UART, SPI, CAN, memories, ADCs/DACs, and interrupt controllers etc. In order to interface with such devices, almost all microprocessors have dedicated interfaces that can be programmed as input or output according to user applications. Nowadays, most widely used digital interface for data handling in microprocessor is General Purpose Input/ Output (GPIO) Coprocessor. GPIO coprocessors relieve microprocessor of responsibilities of handling various input/output interfaces and in the meantime perform other meaningful computations. In this research work, a GPIO coprocessor IP core has been designed and functionally verified. The performance analysis of GPIO has been performed using different priority implementation techniques. The priorities of the different peripherals that are interfaced with the GPIO interfaces are configurable using arbitration technique. The arbitration techniques used are static fixed priority, TDMA based, and centralized arbiter with dynamic priority. The GPIO IP core has been analyzed with and without an arbitration algorithm. The delay for executing with or without arbitration is computed. The design is described using Verilog HDL and verified using Xilinx ISim simulator. The delay for the GPIO module using centralized arbiter with dynamic priority is 10.557 ns. The delay computed for the static fixed priority is less as compared to TDMA based and centralized arbiter with dynamic priority i.e. 8.357 ns. The simulation results validates that by using suitable arbitration algorithm as per requirement of application, the performance of coprocessor IP core can be enhanced by 21%.