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Study of FinFET Based SRAM Cells


Affiliations
1 Department of Electronics and Communication Engineering, Punjabi University, Patiala, India
 

This presents the transistors have been shrinking exponentially size and therefore the transistors in a single microelectronic chip have been rising exponentially. In the current generation of transistors, the exponential reduce in transistor size can continue. This generation is multi gate transistors. Fin FETs are the most appealing option due to their better scalability and options for advance SRAM performance. Fin FET based 6T SRAM cells manufactured with pass gate feedback attain significant developments in the cell read stability without area penalty. The write ability can be improved on the use of pull up writing gating with a separate write word line. In 9T SRAM cell, an appropriate read operation is given by overpowering the drain induced barrier lowering effect and controlling the body source voltage change.

Keywords

FinFET, FinFET Structure, SRAM, Multi Gate Transistor, 6T SRAM Cell, SRAM Read/Write Margin, 9T SRAM Cell, Performance Enhancement Techniques.
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  • Study of FinFET Based SRAM Cells

Abstract Views: 150  |  PDF Views: 0

Authors

Sundeep Kaur
Department of Electronics and Communication Engineering, Punjabi University, Patiala, India
Mandeep Kaur
Department of Electronics and Communication Engineering, Punjabi University, Patiala, India

Abstract


This presents the transistors have been shrinking exponentially size and therefore the transistors in a single microelectronic chip have been rising exponentially. In the current generation of transistors, the exponential reduce in transistor size can continue. This generation is multi gate transistors. Fin FETs are the most appealing option due to their better scalability and options for advance SRAM performance. Fin FET based 6T SRAM cells manufactured with pass gate feedback attain significant developments in the cell read stability without area penalty. The write ability can be improved on the use of pull up writing gating with a separate write word line. In 9T SRAM cell, an appropriate read operation is given by overpowering the drain induced barrier lowering effect and controlling the body source voltage change.

Keywords


FinFET, FinFET Structure, SRAM, Multi Gate Transistor, 6T SRAM Cell, SRAM Read/Write Margin, 9T SRAM Cell, Performance Enhancement Techniques.