Design and Analysis of Low Leakage 1-Bit Adder for Inexact Computing

In most of the digital applications faster speed and low power are the basic requirements. Adders are the basic elements which are widely used in digital systems. Carry select adders (CSLA) are the fastest adder used in many advanced arithmetic circuits to perform the fast calculations in arithmetic circuits. To enhance the speed and to reduce the leakage power we have used approximation technique in CSLA. This work evaluates the comparison of the conventional 1-bit full adder with proposed 1-bit approximate adder in terms of average power, PDP, delay, leakage power and number of transistors. All the Circuits are designed using Tanner EDA tool v13.0 and simulation are performed on H-Spice tool at 500MHz frequency using 45nm technology at supply voltage of 1.1V. Result shows there is improvement in delay, leakage power and number of transistors.