A Study of Full Adder Circuits: from Power and Speed of Operation Perspective

In this paper, we review various design techniques for full adder circuits as these circuits are basic building blocks of many arithmetic circuits. Different techniques are used for low power in full adders. Analysis is based on some simulation parameters like number of transistors, power, delay, power delay product and different technologies at different supply voltages. This paper contributes to a better knowledge of the behaviour of conventional CMOS and CPL full-adder circuit when low voltage, less delay, low power or small power delay products are of concern. This paper will help the circuit designers to select the full adder that satisfies their application.