A Novel High-Speed, Higher-Order 128 bit Adders for Digital Signal Processing Applications Using Advanced EDA Tools

In digital adders, the speed of addition is limited by the time required to transmit a carry through the adder. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. Now days we use the very High Speed IC Designs In that designs we required very High Speed Structures. Parallel prefix adder is the most flexible and widely used for binary addition. Parallel Prefix adders are best suited for VLSI implementation. Numbers of parallel prefix adder structures have been proposed over the past years intended to optimize area, fan-out, logic depth and inter connect count. This paper presents a new approach to redesign the basic operators used in parallel prefix architectures. Based on this modification 8, 16, 32, 64 and 128-bit Kogge-Stone Parallel Prefix Adders architectures have been developed and compared with the regular and Modified CSLA architecture. The modified CSLA design has reduced area and Power as compared with the regular CSLA but delay is increased. The Proposed Kogge-Stone adder has less delay when compared with regular and modified CSLA. This work estimates the performance of the proposed designs in terms of delay, area are implemented in Xilinx ISE.