Research Cell: An International Journal of Engineering Sciences

Anubhav Sharma ¹, Shashank Kamthan ¹, Aby K. George ¹, Amjad Almatrood ¹, Harpreet Singh ¹, Harinder Pal Singh ²

Affiliations
1 College of Engineering, Wayne State University, Detroit, MI, US
2 Dept of Technical Education, Government of Punjab, IN

Abstract

Human heart is a very important part of body. Its proper functioning is extremely important for the survival of human being. Quite often, the heart does not function properly owing to one reason or the other. The primary reason for such a malfunctioning of heart could be due to some of the faulty and abnormal cells in heart. Generally, the photo-techniques are used to destroy such abnormal cells. However, such techniques are not much effective. Currently, laser techniques are used to destroy malfunctioning cells of the heart. The basic idea about these techniques is that with the help of a laser beam, some particles are sent to the cells of heart, so that only the abnormal cells get destroyed while retaining the normal or healthy cells of the heart. Further, the paper also demonstrates a procedure for applying a laser beam for a specified time. The procedure is developed in Verilog software. The Verilog program is then implemented on Field Programmable Gate Array (FPGA), and the testing of this program is done. The developed circuit in the present paper is expected to be useful for a number of applications indifferent industries.

Keywords

Digital Chip, MATLAB, HDL, Cadence, FPGA, Laser Beam, Ablation of Heart.

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Sairam Gowrisankar ¹, Amjad Almatrood ¹, Aby K. George ¹, Harpreet Singh ¹, Harinder Pal Singh ²

Affiliations
1 College of Engineering, Wayne State University, Detroit, MI, US
2 Dept of Technical Education, Government of Punjab, IN

Abstract

There has always been anincreasing interest in the development of new arithmetic processors. The objective of this paper is to describe the hardware implementation of a pipelined arithmetic processorpublished previously, which can add, subtract,multiply,divide,square and square ischolar_main the binary numbers. The processor described resulted in 46input/output pins.The MOSIS and cadence fabrication technology generally allow up to 40 pins. In this paper hardware implementation of arithmetic processor is taken up so that processor chip can be developed by 40 pins. This hardware implementation will lead to better implementation of handling input, output pins for future processors. The hardware implementation of the modified array has been done using Simulink and tested. It is hoped that this research will lead to the design and VLSI implementation of new arithmetic processor.

Keywords

Arithmetic processor, Digital Chip, MATLAB, Pipeline Array, Simulink.

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