Research Cell: An International Journal of Engineering Sciences

Gagandeep Kaur ¹, Candy Goyal ¹

Affiliations
1 Electronics and Communication Section, Yadavindra College of Engineering, Talwandi Sabo, IN

Abstract

As the technology is shrinking day by day, energy and leakage power becoming a critical parameter for modern VLSI design. To full fill the demand and challenge of customer industry is demanding circuits with low power and high performance. In this paper, we have designed 64-bit modified carry select adder by using 6T MUX, 3TAND, 3T XOR and 5Thalf adder configurations which has better performance parameter as compared to the existing design in the literature. To evaluate the performance of modified architecture of carry select adder, extensive simulations are performed by using different bit pattern in T-spice. Result shows that 16-bit carry select adder having improvement in delay upto 34% and average power improves upto 91% and power delay product 92%. The design is extended up to 64bit Carry Select Adder. Results show that by modified Carry select adderconsume lesser average power and power delay product.

Keywords

BEC, RCA, SQRT-CSA,MUX and Power Aware.

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Jagjeet Sharma ¹, Candy Goyal ¹

Affiliations
1 Electronics and Communication Engg Section, Yadavindra College of Engineering, Talwandi Sabo, IN

Abstract

In this paper, a low power and high speed 16x16 Vedic Multiplier is designed using modified carry select adder. Modified Carry Select Adder employs a multiplexer and XOR gate based circuit on the intermediate stages instead of BEC and multiplexer which gives low power and high speed of operation. Vedic multiplier is based on the sutra "Urdhva-Tiryakbhyam" (Vertically and crosswise). It is one of the sutras of Vedic mathematics for multiplication. This sutra used both for decimal multiplication and binary multiplication. In this paper, the main goal is to optimize power and speed of multiplier. Simulation result shows that the proposed architecture achieves advantages in terms of PDP (Power delay product) and latency. The latency count improves as compared to the Dadda multiplier. All the Simulations are carried out in H-Spice at 32nm process technology.

Keywords

Carry Select Adder, Vedic Multiplier, Ripple Carry Adder, Binary to Excess Converter, Urdhva-Tiryakbhyam.

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Ramanbir Sidhu ¹, Candy Goyal ¹

Affiliations
1 Deptt. of Electronics and Communication, Yadavindra College of Engineering, Talwandi Sabo, IN

Abstract

In this paper we have presented three 1-bit full adder cells namely Conventional adder, Transmission gate based adder and 14T adder in dynamic logic style. One bit adder circuits are used to design 4-bit, 8-bit and 16-bit ripple carry adder circuit. In these circuits we have used clock to switch ON and OFF the circuit during evaluation and standby mode, respectively. It helps in improving the performance parameters as compared to the dynamic multi-output logic style in which two PMOS transistors are used to charge the outputs in precharge phase and one NMOS transistor to discharge the output during evaluation phase. Simulation result shows improvements in delay, average power and PDP at 500MHz frequency at 32nm technology using 1.0 voltage supply. Result shows that among proposed dynamic adders 14T dynamic adder has best performance parameter as compared to conventional and transmission gate based adder.

Keywords

H.A(Half adder), CONV (Conventional), TG(Transmission Gate), CMOS(Complementary Metal Oxide Semiconductor), PDP(Power Delay Product).

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Khushveen Sidhu ¹, Candy Goyal ¹

Affiliations
1 Electronics and Communication Engineering, Yadavindra College of Engineering, Talwandi Sabo, IN

Abstract

Adders are one of the basic components in most of the digital systems. Optimization of these adders can improve the performance of the entire system. In this paper we present a multiplexer based hybrid adder to reduce leakage power. To reduce the leakage power we have used the transistor stacking technique. We have compared the conventional multi-level adder and hybrid adder in terms of delay, average power, leakage power and PDP. All the simulations are done using Tanner Tool v13.0 at 500MHz frequency in 22nm technology at a supply voltage of 1.0V. Simulation results show the decrease of leakage power in hybrid adder.

Keywords

HAU (Hybrid Adder Unit), CLA (Carry Look Ahead Adder), CSA (Carry Skip Adder), CMOS (Complementary Metal Oxide Semiconductor), VLSI (Very Large Scale Integration), PDP (Power Delay Product).

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Savinder Kaur ¹, Candy Goyal ¹

Affiliations
1 Electronics and Communication Section, Yadavindra College of Engineering, Talwandi Sabo, IN

Abstract

In most of the digital applications faster speed and low power are the basic requirements. Adders are the basic elements which are widely used in digital systems. Carry select adders (CSLA) are the fastest adder used in many advanced arithmetic circuits to perform the fast calculations in arithmetic circuits. To enhance the speed and to reduce the leakage power we have used approximation technique in CSLA. This work evaluates the comparison of the conventional 1-bit full adder with proposed 1-bit approximate adder in terms of average power, PDP, delay, leakage power and number of transistors. All the Circuits are designed using Tanner EDA tool v13.0 and simulation are performed on H-Spice tool at 500MHz frequency using 45nm technology at supply voltage of 1.1V. Result shows there is improvement in delay, leakage power and number of transistors.

Keywords

CSLA (Carry Select Adders), RCA (Ripple Carry Adder), DSP (Digital Signal Processing), MA (Mirror Adder), FA (Full Adder), VLSI (Very Large Scale Integration), CMOS (Complementary Metal Oxide Semiconductor), PDP (Power Delay Product).

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