Research Cell: An International Journal of Engineering Sciences

Sunil Kumar ¹, Gurmohan Singh ², Manjit Kaur ¹

Affiliations
1 ACS Division, Centre for Development of Advanced Computing (C-DAC), Mohali-160071, IN
2 DEC Division, Centre for Development of Advanced Computing (C-DAC), Mohali-160071, IN

Abstract

This paper describes the design and implementation of ECG signal processing on FPGA. Lot of research work has been carried out for implementation of ECG signal processing circuitry on FPGA. In this research work all the work is carried out using Xilinx Spartan-3E FPGA starter kit which is taken as a central processing unit. On board Programmable preamplifier, ADC and quad DAC on Spartan-3E FPGA kit have been employed for amplification, A/D conversion and D/A conversion respectively. To generate the necessary control signals for on board Pre-amplifier, A/D converter and D/A Converter, we have designed different HDL modules. The digital output of A/D converter is applied to the low pass FIR digital filter for processing the ECG signals. All the designed modules are integrated in a single TOP level entity. All modules are designed, functionally verified, synthesized, placed & routed using Xilinx 14.3i ISE tool. The functional verification has been performed using Model Sim simulator.

Keywords

ECG, VHDL, ADC, DAC, Pre-Amplifier, FIR Filter, Spartan-3E, FPGA.

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Priyanka ¹, Manjit Kaur ¹, Gurmohan Singh ²

Affiliations
1 ACS Division, C-DAC, Mohali-160071, IN
2 DEC Division, C-DAC, Mohali-160071, IN

Abstract

One of the key features of a microprocessor is to interact with and control peripheral devices. These input/output interfaces may be DMA, UART, SPI, CAN, memories, ADCs/DACs, and interrupt controllers etc. In order to interface with such devices, almost all microprocessors have dedicated interfaces that can be programmed as input or output according to user applications. Nowadays, most widely used digital interface for data handling in microprocessor is General Purpose Input/ Output (GPIO) Coprocessor. GPIO coprocessors relieve microprocessor of responsibilities of handling various input/output interfaces and in the meantime perform other meaningful computations. In this research work, a GPIO coprocessor IP core has been designed and functionally verified. The performance analysis of GPIO has been performed using different priority implementation techniques. The priorities of the different peripherals that are interfaced with the GPIO interfaces are configurable using arbitration technique. The arbitration techniques used are static fixed priority, TDMA based, and centralized arbiter with dynamic priority. The GPIO IP core has been analyzed with and without an arbitration algorithm. The delay for executing with or without arbitration is computed. The design is described using Verilog HDL and verified using Xilinx ISim simulator. The delay for the GPIO module using centralized arbiter with dynamic priority is 10.557 ns. The delay computed for the static fixed priority is less as compared to TDMA based and centralized arbiter with dynamic priority i.e. 8.357 ns. The simulation results validates that by using suitable arbitration algorithm as per requirement of application, the performance of coprocessor IP core can be enhanced by 21%.

Keywords

GPIO, Arbitration Algorithm, TDMA, Round Robin, Centralized Arbiter.

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