Research Cell: An International Journal of Engineering Sciences

Sandeep Singh ¹, Parminder Singh Jassal ¹

Affiliations
1 ECE Section, Yadavindra College of Engineering, Talwandi Sabo, IN

Abstract

This paper presents the implementation of RSA algorithm design using VHDL. The Xilinx ISE 14.1 is used with device Spartan-3. In [1], the RSA encryption technique is implemented by using right to left binary radix-2 montmgomery multiplier. This paper presents the implementation of encryption technique by using left to right radix-2 montmgomery multiplier. The modular exponentiation is used for encryption and decryption of RSA algorithm. The device utilization is improved by 14%. The delay is improved by 2%. The frequency of the implementation is 79.546 MHz and is increased by 4.5%. Hence, the presented work is area and delay efficient than previous work.

Keywords

Encryption, RSA, FPGA, VHDL, Delay.

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Viney Pal Bansal ¹, Parminder Singh Jassal ¹

Affiliations
1 ECE Section, Yadavindra College of Engineering, Talwandi Sabo, IN

Abstract

Data security has become the major issue now in these days, especially for the use of internet. So, to protect the IP-based data, we must have to use strong cryptographic techniques. Blowfish cryptosystem is one of the strong and fast algorithms used for cryptography. This paper presents the implementation of Blowfish algorithm using VHDL. The device Virtex 4 is used with Xilinx ISE 14.1. The device utilization is improved by 1% and delay is reduced by 2ns in this work.

Keywords

Encryption, Blowfish, FPGA, VHDL, Internet.

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