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Authors
Affiliations
1 Indian Institute of Technology, Roorkee, IN
2 Indian Institute of Technology, Roorkee,
Uttarakhand, IN
3 Indian Institute of Technology, Roorkee, Uttarakhand, IN
Source
Programmable Device Circuits and Systems, Vol 1, No 3 (2009), Pagination: 39-46
Abstract
Register file is one of the most power hungry components in the processor consuming about 20% of the processor power, because it contains large capacitances on bit lines, word lines,address lines, and storage cell array and is frequently accessed. This paper presents a complete study of register file based on adiabatic logic at 90nm CMOS process. A 32 x 32 register file using adiabatic complementary pass-transistor logic (ACPL) has been designed. All the circuits expect for storage cell employ ACPL circuits and storage cell is based on conventional memory (SRAM cell). Since register file consists of large capacitances, the minimization of power consumption is made by choosing optimal size of ACPL circuits for driving large capacitances. For comparison, two other register file based on same organization were simulated using CPAL and conventional CMOS logics. Simulation results shows that adiabatic CPL register file achieves power saving of 30% with CPAL and 91% to 95% with conventional CMOS logic for clock frequencies ranging from 50 to 500MHz. Since power consumption is a function of output load capacitance and supply voltage, we have also simulated these register file for various supply voltages and load capacitances.
Keywords
Adiabatic Logic, ACPL, Low Power, Register File, SRAM.
