Informatics Publishing Limited

K. Jagannadha Naidu ¹, Harish M. Kittur ¹

Affiliations
1 VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

Objectives: A novel On Chip switched capacitor architecture to produce multiple voltages with high switching frequency and low ripple voltage. Methods: The proposed architecture uses integration of more than one converter topology to produce the scalable output voltage. The converter consists of MOSFET switches and MOS charge-transfer capacitors. The control circuitry was designed completely with digital domain to reduce static power consumed. Findings:The simulation of the scalable DC-DC converter was performed using TSMC 90nm Technology .The maximal efficiency of 80% was achieved for different topologies with 364 MHz switching frequency. Improvements: The load driving capacity of this converter was up to 5uW.

Keywords

DC-DC, DVS, High Frequency, Ripple Voltage, Voltage Converter

Full Text

   

S. Ravi ¹, Subhajit Sinha ¹, R. Adithyan ¹, Harish M. Kittur ¹

Affiliations
1 VLSI Division, SENSE, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

Background/Objectives: As the complexity of system on chip increases the timing sign-off becomes a challenging task for STA (Static Timing Analysis) engineer. Methods/Statistical analysis: Due to the wide usage of IP’s, change in power and skew may occur among different regions of chip. To address this issue clock gating and zero skew algorithms are mainly used. It is good design idea to turn off the clock when it is not needed. Findings: This paper proposes  a new  NOR/OR  cells with different driving strengths and a new tunable delay elememt . These designed cells can be  used in automatic clock gating which is supported by modern EDA tools. The proposed method of clock buffers with different sizes are designed and compared with ISCAS89 Benchmark circuits (s35932, s38417, and  s38584).These components are designed and tested using Cadence ICFB and SOC encounter P&R tool. Applications/Improvements: This clock gating elements can be used in any System-on-a-Chip (SoC) application where minimum skew is required.

Keywords

Clock Gating, Delay Matching, Skew, Tunable Delay, Type Matching

Full Text

   

V. Mohammed Zackriya ¹, Anurag Verma ¹, Harish M. Kittur ¹

Affiliations
1 School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

Power dissipation due to memories has become a major concern of modern digital design. Scaling of CMOS technology has lead to short channel effects. Here CAM cells are designed using FinFET which have better gate control over drain to source current. The CAM cells designed with 30nm LG are used in multi-segment hybrid CAM architecture. The results are compared with the original hybrid CAM. It is observed that the energy metric of proposed architecture is 7% less compared to hybrid CAM.

Keywords

Content-Addressable Memory (CAM), FinFET, Hybrid-Type CAM.

Full Text