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Khare, Kavita
- A Study of Channel Estimation Techniques Based on Pilot Arrangement in OFDM Systems
Authors
1 Maulana Azad National Institute of Technology, Bhopal (M.P), IN
2 Electronics and Communication Department at Maulana Azad National Institute of Technology, Bhopal (M.P), IN
3 Computer Science and Engineering Department at Maulana Azad National Instt of Technology, Bhopal (M.P), IN
Source
Wireless Communication, Vol 3, No 2 (2011), Pagination: 114-120Abstract
The channel estimation techniques for OFDM systems based on pilot arrangement are investigated. The channel stimation based on comb type pilot arrangement is studied through different algorithms for both estimating channel at pilot frequencies and interpolating the channel. The estimation of channel at pilot frequencies is based on LS and LMS while the channel interpolation is linear interpolation, second order interpolation, low-pass interpolation, spline cubic interpolation, and time domain interpolation. Time-domain interpolation is obtained by passing to time domain through IDFT, zero padding and going back to frequency domain through DFT. In addition, the channel estimation based on block type pilot arrangement is performed by sending pilots at every sub-channel and using this estimation for a specific number of following symbols. We have also implemented decision feedback equalizer for all sub-channels followed by periodic block-type pilots. We have compared the performances of all schemes by measuring bit error rate with 16QAM, QPSK, DQPSK and BPSK as modulation schemes, and multipath Rayleigh fading and AR based fading channels as channel models. The simulation results show that combtype pilot based channel estimation with low-pass interpolation performs the best among all channel estimation algorithms.
Keywords
Channel Estimation, OFDM, Pilot Carrier, Rayleigh Fading.
- Comparison of Leakage Current at Deep Sub Micron Technologies in CMOS Digital Circuit
Authors
1 Department of Electronics and Communication Engineering, MANIT, Bhopal, IN
Source
Programmable Device Circuits and Systems, Vol 6, No 5 (2014), Pagination: 147-149Abstract
High leakage current in Deep-Sub Micron (DSM) regimes is becoming a significant contributor to power dissipation of CMOS circuit parameters are reduced. This paper focusing on the leakage current which is highly dependent on potential applied on the transistors gate. That's why it can be said that input of the logic gate is able to control the leakage of the gate appropriately during run time of the device. Consider the input vector methodology to analyse NAND logic with 2 inputs using HSPICE simulator with BPTM technologies (i.e. 180nm, 130nm, 90nm, 65nm, 45nm) model. It gives the similar behaviour of leakage current with every technology models. Hench we can shift the logic gate input with its Minimum Leakage Vector (MLV) during run time of the device. Above technique is process parameter independent and there is no need of any extra power supply to reducing the leakage.Keywords
Leakage Current, MLV, Input Vector Control.- A Wide Range 4.5 GHz VCO Using 45nm CMOS Technology
Authors
1 Electronics & Communication Engineering Department, T.I.T. College, Bhopal, IN
2 Electronics & Communication Engineering Department, MANIT, Bhopal, IN
Source
Programmable Device Circuits and Systems, Vol 4, No 3 (2012), Pagination: 155-159Abstract
This paper presents design of ring oscillator based voltage controlled oscillator for wide frequency range applications requiring on-chip oscillators to generate clocks at low power. The structure and operating principle of ring oscillator have been described and the expression for the frequency of oscillation of a CMOS delay cell based conventional ring oscillator is presented. The VCO is designed and simulated in 45nm CMOS technology with BSIM 4.3.0 MOSFET model, level 54 parameters using SPICE simulator. At constant supply voltage (VDD) of 1V, as input control voltage varies from 0.3V to 1V in a step of 0.2V the output frequency changes from 0.54GHz to 4.5GHz, thus providing a maximum tuning range of 88%. The total power dissipation is of the order of 60 μW, with center drain current of 60.0 μA for current mirror formed with MOSFETs M3 & M4. The Phase Noise obtained for the proposed design is 0.116mV/Hz1/2 at 1MHz.Keywords
Voltage Controlled Oscillator (VCO), Tuning Range, Phase Noise, CMOS Inverter, Power Dissipation.- Design and FPGA Implementation of DDR3 SDRAM Controller for High Performance
Authors
1 Dept. of Electronics and Communication, M.A.N.I.T, Bhopal, IN
Source
AIRCC's International Journal of Computer Science and Information Technology, Vol 3, No 4 (2011), Pagination: 101-110Abstract
The demand for faster and cheaper memories has been increasing by the day. Hence, these memory devices are rapidly developing to give high density and high memory bandwidths. However, with the increase in technology, complexity of instructions to control the memory devices also increases. In this paper, a specific purpose DDR3 Controller is described. This paper presents the overall architecture of the DDR3 Controller. Also the advantages of DDR3 over DDR2 and DDR are discussed.Keywords
DDR3, VHDL, Xilinx, FPGA.Full Text
