Informatics Publishing Limited

K. Rekha ¹, R. Udaiya Kumar ¹

Affiliations
1 Department of ECE, V.L.B. Janakiammal College of Engineering and Technology, Kovaipudur, Coimbatore–641042, Tamil Nadu, IN

Abstract

Cryptanalysis of symmetric and asymmetric ciphers is computationally extremely demanding. Since the security parameters of almost all practical crypto algorithms are chosen such that attacks with conventional computers are computationally infeasible. The DES algorithm is the most widely used private-key encryption algorithm. DES is a block cipher, which takes 64-bit input and 64-bit key. Since DES is easily breakable, the advanced version of DES namely Advanced Encryption Standard (AES) is used for implementation. The data block length is 128-bits and the key length may be 128-bits, 192-bits and 256- bits. In this paper, AES algorithm is implemented in Field Programmable Gate Arrays [FPGA] for optimizing area. Two architectures of AES are compared here. In one architecture, look-up-table method of s-box and general mix-column architecture are used and in other composite field arithmetic method of s-box and light weight mix-column architecture are used.

Keywords

AES, S-box, Mix Column, FPGA.

Full Text

     

M. Nithyajeevi ¹, R. Udaiya Kumar ¹, S. Vimal Raj ²

Affiliations
1 Department of ECE, V.L.B. Janakiammal College of Engineering and Technology, Kovaipudur, Coimbatore-641042, Tamil Nadu, IN
2 Department of EEE, V.L.B Janakiammal College of Engineering and Technology, Coimbatore-641042, Tamil Nadu, IN

Abstract

This paper is aimed at testing a device under test (DUT) with embedded built-in self-test (BIST) capability. The embedded BIST technique has the capability to satisfy specified testability requirements and to generate the lowest-cost with the highest performance implementation. Linear Feedback Shift Register (LFSR) is used to replace the expensive testers to generate pseudo random test pattern to DUT while Orthogonal Code Convolution method acts as output compact analyzer and is able to compact the DUT output response into a manageable signature size. DUT with BIST capability contributes additional 30% hardware overhead but is somehow reasonable considering the test performance obtained. The ability of the BIST block provides high fault coverage. Moreover to increase the fault coverage parity bit is introduced for error checking. To overcome power dissipation clock gating is proposed to reduce number of transitions during off state so that clock signals can be kept in sleep mode to reduce power consumption.

Full Text