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Source
International Journal of Innovative Research and Development, Vol 3, No 5 (2014), Pagination:
Abstract
The area and power efficiency is very important for every circuit and its applications. Here we we present an efficient architecture for the implementation of a delayed least mean square adaptive filter. By using improved adder structure the area power efficiency can be increased. with this the area delay product (ADP) and energy delay product(EDP) can be saved in a considerable amount. Ripple carry adder is used here and the main advantages are lower power consumption as well as compact layout giving smaller chip area..
Keywords
Adders, Adaptive filter, LMS algorithm, fixed point arithmetic
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