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Ravindrakumar, S.
- A High CMRR Front End Design with AC Coupling for QRS Detection
Abstract Views :341 |
PDF Views:1
Authors
Affiliations
1 Vivekananda College of Engineering for Women, Tiruchengode, TN-637 205, IN
1 Vivekananda College of Engineering for Women, Tiruchengode, TN-637 205, IN
Source
Programmable Device Circuits and Systems, Vol 1, No 3 (2009), Pagination: 34-38Abstract
The noise coupling and artifact removal for ECG front end is proposed, Electrocardiography signals may be corrupted by various kinds of noise. Different noise sources occurring due to motion artifact, power line interference, instrumentation noise etc., is analyzed and proper approach is made. A filtering approach is done for the removal of artifact, offset noise and unwanted frequencies.The CMRR of the instrumentation amplifier is improved by AC coupling with a DC restoration loop along with the DRL circuit. A DRL (Driven Right Leg) is designed to reduce the common mode noise. The proposed model has a CMRR of 120dB.As the noise is the major phenomenon in the filter designing the filters are choose such that they have a low sensitivity. The sensitivity of some important RC-active filter realizations including Gyrator are derived and compared. According to the application of ECG monitoring, among the different configuration the low sensitivity filter is chosen w.r.t. to experimental results. Practical realization is done for low-pass, high pass and notch filter for different Q and β and the results are checked.The circuits used have zero sensitivity for resistors and capacitors.
Keywords
Noise Coupling, ECG front End, ECG Signal Conditioning, Filters, Low Sensitivity Filters.
- Error Compensation Technique for 90nm CMOS Fixed-Width and Area Efficient Booth Encoding Multiplier
Abstract Views :142 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Sri Shakthi Institute of Engineering and Technology, IN
2 Department of Electronics and Communication Engineering, Malla Reddy College of Engineering and Technology, IN
3 Nano Electronics and Integration Division, IRRD Automatons, IN
1 Department of Electronics and Communication Engineering, Sri Shakthi Institute of Engineering and Technology, IN
2 Department of Electronics and Communication Engineering, Malla Reddy College of Engineering and Technology, IN
3 Nano Electronics and Integration Division, IRRD Automatons, IN
Source
ICTACT Journal on Microelectronics, Vol 5, No 3 (2019), Pagination: 820-824Abstract
An area efficient, fixed width multiplier using booth encoding is done in this work. The work is further extended to accommodate the error correction feature. As in many signal processing products fast and efficient processing elements are required, the demand increases day by day. This work is one such finding to meet the standard of today’s contemporary technology. The proposed methodology suits well for the discrete cosine transform application. A new multiplier architecture using booth encoding is done. The architecture includes a tree based carry save reduction unit with parallel prefix adder and the compensation circuit. The work is carried out in 180nm technology using predictive technology models. The circuits are implemented using SPICE models and the results are obtained. For equal probability the inputs of different blocks are kept ‘1’ or ‘0’ in equal numbers. The frequency of operation is 100MHz. The proposed design will be compared with the existing methods. The robustness will be checked using skewed distribution. The project will be further extended to design for high speed and advanced technology of 90nm in future.Keywords
Multiplier, Carry Save Reduction, Booth Multiplier, Error Compensation.- CMOS Based Driver Tree Design for Microprocessor Clock Distribution Units Iin Biomedical Image Processing Circuits
Abstract Views :130 |
PDF Views:0
Authors
V. Sujatha
1,
S. Ravindrakumar
2,
D. Sasikala
3,
V. M. Senthil Kumar
4,
N. V. Kousik
5,
Jayasri Subramaniam
6
Affiliations
1 Department of Electronics and Communication Engineering, Shree Sathyam College of Engineering and Technology, IN
2 Department of Biomedical Engineering, Sri Shakthi Institute of Engineering and Technology, IN
3 Department of Electronics and Communication Engineering, Muthayammal Engineering College, IN
4 Department of Electronics and Communication Engineering, Malla Reddy College of Engineering and Technology, IN
5 Department of School of Computing Science and Engineering, Galgotias University, IN
6 Division of Computing, University of Northampton, GB
1 Department of Electronics and Communication Engineering, Shree Sathyam College of Engineering and Technology, IN
2 Department of Biomedical Engineering, Sri Shakthi Institute of Engineering and Technology, IN
3 Department of Electronics and Communication Engineering, Muthayammal Engineering College, IN
4 Department of Electronics and Communication Engineering, Malla Reddy College of Engineering and Technology, IN
5 Department of School of Computing Science and Engineering, Galgotias University, IN
6 Division of Computing, University of Northampton, GB
Source
ICTACT Journal on Microelectronics, Vol 7, No 1 (2021), Pagination: 1080-1084Abstract
The transmission of clock signal is done across the integrated circuit in the presence of buffers and wires in synchronous biomedical systems on-chip architectures. This paper presents the investigation of the driver tree architecture to be used in microprocessor and DSP processors for biomedical image processing applications for clock distribution. In system on chip architecture this design plays an important role. Several clock distribution units like parallel, H-Bridge configurations were implemented in past. A new buffer is designed for the improvement of driving capability in clock distribution. This paper presents the CMOS based clock distribution circuit with better power and drive current. The parameters like power and current are investigated. Predictive technology models for CMOS 90nm technology are used.Keywords
CMOS, Current Driver, Clock Driver, H-Bridge, Buffer, Power.References
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- Ravindrakumar, Joselyn, “Design of Low Power Blink Detector for Minimally Invasive Implantable Stimulator (SOC) using 180nm Technology”, Advances in Intelligent and Soft Computing, 2014.
- Ravindrakumar, Joselyn, “Design of New Implantable Stimulator Chip (SoC) for Non-Invasive/Minimally Invasive Biomedical Application”, Proceedings of International Conference on Communications and Signal Processing, pp. 1-5, 2014.
- V.M. Senthilkumar, A. Muruganandham, S. Ravindrakumar and N.S. Gowri Ganesh, “FINFET Operational Amplifier with Low Offset Noise and High Immunity to Electromagnetic Interference”, Microprocessors and Microsystems, Vol. 71, pp.1-22, 2019.
- V.M. Senthilkumar, S. Ravindrakumar and D. Nithya,“A Vedic Mathematics Based Processor Core for Discrete Wavelet Transform using FinFET and CNTFET Technology for Biomedical Signal Processing”, Microprocessors and Microsystems, Vol. 71, pp.2221-2228, 2019.
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