Informatics Publishing Limited

Abstract

Global System for Mobile Communications (GSM) is the most widely used cellular technology in the world. Main objective in mobile communication systems is security of data exchanged. GSM uses several cryptographic algorithms for security like A5/1, A5/2 and A5/3. From extensive literature survey it has been found that these algorithms are cracked by various practical attacks so these algorithms do not provide sufficient levels of security for protecting the confidentiality of GSM therefore it is desirable to secure data by additional encryption. In this paper we have proposed additional encryption by implementing DES, TripleDES, and AES algorithms on GSM Network. For testing these algorithms on GSM,sending and receiving code is simulated by doing GSM encoding and decoding. This paper also analyzes the effectiveness of these algorithms against brute force attack implemented in MATLAB environment.

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Abstract

Processor simulator models are the integral part of nearly all modern SOC/ASIC virtual platforms, as they let the software development team to progress without the dependency on the silicon tape-out time. Important considerations while developing an Instruction Set Simulator are speed and accuracy, which generally comes at the cost of decreased granularity of the different stages of instruction life cycle. Mainstream processor ISS virtual models do not implement the pipelines, as it’s a bottleneck to the performance and increases code complexity when implemented in the languages as C, C+. This eradicates ISS model’s scope for system level program development like compiler design and architecture exploration of new processors, limiting its use only for pre-silicon software testing. In this paper we present a novel technique to implement pipelines using multi-threaded SystemC high level hardware modeling language, that provides better granular accuracy and enhanced instruction execution performance efficiency to the processor ISS over a similarly modeled no pipeline version of the ISS. Classic RISC 3 stage pipeline is taken as a reference for this design and implementation.

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Abstract

Mainstream processor virtual models do not implement pipelines in their design, as it is considered as an overhead in terms of code complexity and may reduce the performance due to large context switching that will happen in the simulation in effect to handle the notion of concurrent execution of the pipeline algorithm. This problem provides an interesting opportunity to evaluate the performance of a pipelined processor virtual model which is implemented using a multithreaded language and is free of the single thread context switching overhead present in current hardware description programming languages. The novelty of the pipelined processor model and its performance evaluation in different scenarios of loads is described in this paper, and it describes the execution process of the multithreaded SystemC language, which is used for the model’s implementation. The limitations in current multicore implementation of simulation kernel which were faced during the implementation are also analyzed to provide scope for further research and development.

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