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Inthiyaz, Syed
- An Efficient Design of Sequential Digital Circuits to Reduce Soft Errors in Nanoscale CMOS Technology
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Authors
Affiliations
1 M.Tech. Student, Department of E.C.E., K.L. University, Guntur Dt., A.P.,, IN
2 Dept. of ECE, K.L. University, Vijayawada, IN
1 M.Tech. Student, Department of E.C.E., K.L. University, Guntur Dt., A.P.,, IN
2 Dept. of ECE, K.L. University, Vijayawada, IN
Source
International Journal of Engineering studies, Vol 4, No 1 (2012), Pagination: 55-63Abstract
We initiate some soft-error-tolerant Sequential elements which evaluate the benefits and drawbacks of several state-of-the-art designs, and determines optimal designs for advanced technology. The designs induce non-trivial area, power overhead. In modern technologies, logic elements are becoming increasingly vulnerable to soft errors. Several designs today implement extensive error detection and correction. In this design we use smaller and faster transistors. In this work, we will analyze the impact of soft errors on latches and flip-flops in nanoscale CMOS technology. Here each design is compared with a standard, non-SER tolerant latch or flip-flop, and then assess each design based on SER protection, area, and power overhead.Keywords
Reliability, Soft Error, SER, Nanoscale Cmos
References
- Heijman T., “Soft-Error Vulnerability of Sub-100-nm Flip-flops”, IEEE International On-Line Testing Symposium, 2008.
- Baumann R.C., "Radiation-Induced Soft Errors in Advanced Semiconductor Technologies", IEEE Tran. on Device and Materials Reliability, 2005, pp. 305- 316.
- Calin T., Nicolaidis M., Velazco R., “Measurements and Analysis of SERtolerant Latch in a 90-nm Dual-VT CMOS Process”, IEEE Tran. On Nuclear Science, 1996, pp. 2874-2878.
- Hazucha P. et al., “Measurements and Analysis of SER-tolerant Latch in a 90- nm Dual-VT CMOS Process”, IEEE Journal of Solid-State Circuits, 2004, pp. 1536-1543.
- Lin S., Yang H., Luo R., “A New Family of Sequential Elements With Built-In Soft Error Tolerance for Dual-VDD Systems”, IEEE Transactions on Very Large Scale Integration Systems, 2008
- Zhang M. et al., “Sequential Element Design With Built-In Soft Error Resilience”, IEEE Transactions on Very Large Scale Integration Systems, 2006.
- Komatsu Y. et al., “A Soft-Error Hardened Latch Scheme for SoC in a 90nm Technology and Beyond”, IEEE 2004 Custom Integrated Circuits Conference, 2004.
- Das S. et al., “RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance”, IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp. 32-48, 2009.
- Chandras V. and Aitken R., “Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS”, IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008.
- S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, “Robust system design with built-in soft error resilience, ” IEEE Computer, vol. 38, no.2, pp. 43–52, Feb. 2005.
- S. Lin, H. Yang, and R. Luo, “High speed soft-error-tolerant latch and flip-flop design for multiple Vdd circuit, ” in IEEE Comput. Soc. Annu. Symp. VLSI, May 2007, pp. 273–278.
- P. Hazucha and C. Svensson, “Impact of CMOS technology scaling on the atmospheric neutron soft error rate, ” IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2586–2594, Dec. 2000.
- J. E. Knudsen and L. T. Clark, “An area and power efficient radiation hardened by design flip-flop, ” IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3392–3399, Dec. 2006.
- T. Heijmen et al., “Acomprehensive study on the soft-error rate of Flip-Flops from 90-nm production libraries, ” IEEE Trans. Device Mater. [15] Reliab., vol. 7, no. 1, pp. 84–96, Mar. 2007.
- Reliab., vol. 7, no. 1, pp. 84–96, Mar. 2007.
- FPGA Implementation by using XBEE Transceiver
Abstract Views :108 |
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Authors
B. Murali Krishna
1,
M. Siva Kumar
1,
J. Rajesh
1,
Syed Inthiyaz
1,
J. Mounica
1,
M. Bhavani
1,
Choti Nikitha Adidela
1
Affiliations
1 Department of Electronics and Communication Engineering, KL University, Vijayawada – 520002, Andhra Pradesh, IN
1 Department of Electronics and Communication Engineering, KL University, Vijayawada – 520002, Andhra Pradesh, IN
Source
Indian Journal of Science and Technology, Vol 9, No 17 (2016), Pagination:Abstract
Objective: Generally there are numerous approaches to give security information that is being imparted. However, what if the security is assured irrespective of the hackers are from the noise. The Information Security is essential concern towards each communication system. Methods/Analysis: XBee is a PAN technology based on the IEEE 802.15.4 standard. Unlike Bluetooth or wireless USB devices, XBee devices have the ability to form a mesh network between nodes. Meshing is a type of daisy chaining from one device to another. Finding: This technique allows the short range of an individual node to be expanded and multiplied, covering a much larger area. This paper describes a design of desired security for data communication by designing standard algorithm for encryption and decryption. The process occur in this module was based on encryption and decryption. The source information is generated by a bit file and this will be encrypted and is sent to destination through XBee modules. The receiving system will check the data and decrypt according to a specific algorithm and displays on the LED. Applications/Improvement: The present algorithm is implemented in Verilog HD Land simulated using Xilinx ISE simulator tool. The design is implemented on Xilinx Spartan-3 EFPGA development board. This project has applications in encoding and decoding operations for security purposes.Keywords
Decryption, Encryption, Spartan 3E FPGA, Verilog HDL, Xgbee, Xilinx ISE Tool.Full Text
- Analysis of Low Power Conditional Sum Adder
Abstract Views :104 |
PDF Views:0
Authors
M. Siva Kumar
1,
Syed Inthiyaz
1,
V. Narsimha Nayak
1,
M. Bhavani
1,
K. Charan Teja
1,
S. J. S. Rajesh
1,
K. Eswar Reddy
1,
G. Sruthi Keerthana
1
Affiliations
1 Department of Electronics and Communication Engineering, KL University, Vijayawada - 522502, Andhra Pradesh, IN
1 Department of Electronics and Communication Engineering, KL University, Vijayawada - 522502, Andhra Pradesh, IN
Source
Indian Journal of Science and Technology, Vol 9, No 17 (2016), Pagination:Abstract
Objective: To implement high speed arithmetic systems especially conditional sum adder is used. It consists mainly conditional cells and sum cells. Method/Analysis: It contains sum and carry with input 1 and 0. These are used to reduce delay generated by the carry propagator. The advantage using conditional sum adder is addition is much faster. Finding: In this project we are going to deal with the low power conditional sum addition rule. By doing this it will basically reduce the nodes which are present internally and number of multiplexer in the adder design. By implementing this adder in cadence software the power will be reduced and the process can be done by applying clock gating and by without applying clock gating. Novelty/Improvement: For implementing this adder Verilog code is used. And this will be executed in cadence software. Because of using Verilog code, using the digital cadence software.Keywords
Conditional Carry Addition (CCA), Clock Gating, Conditional Sum Adder (CSA), Low Power.Full Text