Refine your search
Collections
Co-Authors
- Y. Varthamanan
- G. Prabhakaran
- V. Kavitha
- A. Nandhini
- E. Logashanmugam
- B. Sheela Rani
- Raju Daniel
- N. Marie Claude
- N. Marie Wilson
- V. Nagarajan
- T. Jaya
- V. J. K. Kishor Sonti
- T. Ravi
- V. Vijayakumar
- P. E. Sankaranarayanan
- S. K. Srivatsa
- V. Saravanan
- M. Govinda Raja Chowdary
- R. Arun Prasath
- Koyi Lakshmi Prasad
- T. Ch. Malleswara Rao
- Terry Thomas
- R. Vinayagasundaram
Journals
- Indian Journal of Advances in Electronic Engineering
- Indian Journal of Science and Technology
- Programmable Device Circuits and Systems
- Digital Signal Processing
- Journal of Advances in Engineering Sciences
- International Journal of Innovative Research and Development
- Journal of Entrepreneurship & Management
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Kannan, V.
- Design and Power Analysis of Novel CNTFET Based Combinational Logic Block for Reconfigurable
Abstract Views :663 |
PDF Views:26
Authors
Y. Varthamanan
1,
V. Kannan
2
Affiliations
1 Sathyabama University, Chennai, Tamilnadu 600119, IN
2 Jeppiaar Institute of Technology, Kunnam, Tamilnadu-631604, IN
1 Sathyabama University, Chennai, Tamilnadu 600119, IN
2 Jeppiaar Institute of Technology, Kunnam, Tamilnadu-631604, IN
Source
Indian Journal of Advances in Electronic Engineering, Vol 1, No 1 (2013), Pagination: 81-88Abstract
This paper discuss about the novel approach of designing combinational logic block using cntfet. Reconfigurable architecture has become increasingly challenging because of high density requirements. Power analysis has been performed using HSPICE simulation software and the results are obtained for the CLB's. Results obtained are encouraging and explores the novel methodologies of FPGA designing.Keywords
Reconfigurable Architecture, CLB, CNTFET, Carbon Nano Tubes, Power Consumption
References
- Dafeng Zhou, Tom J Kazmierski and Bashir M Al-Hashimi, VHDL-AMS implementation of a numerical ballistic CNT model for logic circuit simulation - In IEEE Forum on Specification and Design Languages 2008, Southampton, SO17 1BJ, UK, 2008.
- H. Dai, A. Javey, E. Pop, D. Mann, Y. Lu, "Electrical Properties and Field- Effect Transistors of Carbon Nanotubes," Nano: Brief Reports and Reviews 1, 1 (2006).
- U. Farooq et al., Tree Based Heterogeneous FPGA Architectures, 7 DOI: 10.1007/978-1-4614-3594-5_2, © Springer Science+Business Media New York 2012.
- Bipul C. Paul, Shinobu Fujita, Masaki Okajima, and Thomas Lee.Modeling and analysis of circuit performance of ballistic CNFET. In 2006 Design Automation Conference, San Francisco, CA, USA, 24-28 July 2006.
- V.J.K.Kishor Sonti, V.Kannan, ‘Performance analysis of PHEMT Low Noise Amplifier design Based on RT Duroid Substrate” Vol . 90, issue 3, November-2012, European Journal of Scientific Research, IF: 0.493
- B. Vanzeghbroeck, Principles of semiconductor devices, ecee.colorado.edu/~bart/book/book/chapter3/pdf/ch3_6.pdf.
- www.wikipedia.org
- Design and Analysis of High Gain, Low Power and Low Voltage a-Si TFT based Operational Amplifier
Abstract Views :272 |
PDF Views:0
Authors
G. Prabhakaran
1,
V. Kannan
2
Affiliations
1 Faculty of Electronics and Communication, Sathyabama University, Chennai-600119, Tamil Nadu, IN
2 Jeppiaar Institute of Technology, Sriperumbudur, Kanchipuram District, Kunnam-631604, Tamil Nadu, IN
1 Faculty of Electronics and Communication, Sathyabama University, Chennai-600119, Tamil Nadu, IN
2 Jeppiaar Institute of Technology, Sriperumbudur, Kanchipuram District, Kunnam-631604, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 8, No 16 (2015), Pagination:Abstract
This paper investigates on the design of two stage Operational Amplifier (Op-Amp) with NMOS input at differential stage. This low power Op-Amp designed with Amorphous Silicon Thin Film Transistor (a-Si TFT) and MOS transistor. It is observed that the newly designed TFT Op-AMP operates in low voltage at 3V DC, with high gain, high output impedance and high phase margin and moderate power dissipation. A detailed design procedure is carried-out to design the proposed Op-Amp. HSPICE Circuit Simulator is used for simulation. Obtained results are compared with CMOS Op-Amp which uses the same circuit and design procedure. The output behavior of TFT Op-Amp is also compared with the existing work showing good agreement.Keywords
Amorphous Silicon, CMOS, High Stability, Low Power, Operational Amplifier, Thin Film TransistorFull Text
- Realtime Approach to Enhance Data Acquisition with Task Synchronization
Abstract Views :156 |
PDF Views:5
Authors
V. Kavitha
1,
V. Kannan
2
Affiliations
1 Department of Electrical and Electronics Engineering (ECE) in Dr. MGR Educational and Research Institute, Chennai–600095, IN
2 Jeppiaar Institute of Technology, Kunnam, Tamilnadu, IN
1 Department of Electrical and Electronics Engineering (ECE) in Dr. MGR Educational and Research Institute, Chennai–600095, IN
2 Jeppiaar Institute of Technology, Kunnam, Tamilnadu, IN
Source
Programmable Device Circuits and Systems, Vol 5, No 8 (2013), Pagination: 342-349Abstract
Shared resource problem arises in realtime applications due to the lack of mutual exclusiveness of resource for a task that leads to data corruption and contention. This paper implements kernel activity schemes for effective handling of multiple tasks using RTOS concepts to suit critical applications and concurrent task handling in realtime environment. To protect shared data and to achieve task synchronization, schemes of interrupt enabling/disabling and global variable usage are employed using Priority based Preemptive Task scheduling algorithm in uc/os-II Real Time Operating System on cortex M3 processor. This algorithm is optimum with respect to task execution time and interrupts response. The resultant empirical evidence demonstrates improvement of system performance and response under critical activities.Keywords
Critical Section, Micro/os-II, Priority Scheduling Shared Data Problem, UML Diagram.- Design of a Stable Integrator for Aditya Tokamak
Abstract Views :185 |
PDF Views:1
Authors
Affiliations
1 Sathyabama University, Sholinganallur, Chennai, Tamilnadu, IN
2 Jeppiaar Institute of Technology, Kunnam, Kanchipuram District, IN
3 Institute of Plasma Research, Bhat, Gujrat, IN
1 Sathyabama University, Sholinganallur, Chennai, Tamilnadu, IN
2 Jeppiaar Institute of Technology, Kunnam, Kanchipuram District, IN
3 Institute of Plasma Research, Bhat, Gujrat, IN
Source
Programmable Device Circuits and Systems, Vol 5, No 7 (2013), Pagination: 290-293Abstract
A stable integrator of long duration up to 5s has been designed for Aditya tokamak. In tokamaks, the accurate knowledge about the plasma position has been required for maintaining the distance between plasma and in vessel component. Hence, the value of plasma current, magnetic field and magnetic flux are to be calculated by integrating signals from the magnetic pick up loops. High accuracy integrators are required for the accurate magnetic measurements for long duration signals. The proposed integrator design composed of microcontroller, DAC, integrator and ADC. This design provides a stable output for noisy and drift input signal level up to 5s. The microcontroller has been used to maintain the stability of the output signal and also eliminate the offset induced noise components.Keywords
ADC, Drift, Integrator, Microcontroller, Plasma.- An Efficient Nano Sensor for Strain Sensing and Defect Detection in Engineering Components
Abstract Views :207 |
PDF Views:2
Authors
Affiliations
1 IFET College of Engineering, Villupuram-605108, Tamil Nadu, IN
2 Jeppiaar Institute of Technology, Sriperumpudur, Chennai-631 604, IN
3 Jeppiaar Institute of Technology, Sriperumpudur, Chennai-631604, IN
1 IFET College of Engineering, Villupuram-605108, Tamil Nadu, IN
2 Jeppiaar Institute of Technology, Sriperumpudur, Chennai-631 604, IN
3 Jeppiaar Institute of Technology, Sriperumpudur, Chennai-631604, IN
Source
Programmable Device Circuits and Systems, Vol 5, No 4 (2013), Pagination: 140-143Abstract
This work demonstrates the application of PVDF/CNT composite as strain sensor and defect detector. The PVDF/CNT films were prepared by solution/filtration method and were bonded directly onto specimens by nonconductive adhesive. The two electrodes were connected on to PVDF/CNT films with silver conducting epoxy to reduce contact resistance. Conventional Strain gauge is also attached to other end of the specimen for comparison. For testing purpose 9CR 1MO material is considered and cut into dog bone shaped structures according to ASTM standards. Tensile load is applied by subjecting the specimen in a servo hydraulic test frame .Calibration curves were plotted with change in voltage versus the strain obtained in test specimen. The result shows that there is linear change in voltage across the film when subjected to tension. The defect detection is done using electronic measurement technique. The results shows that the presence of defect was marked by high value of resistance on that particular region and the resistance value was low in non-defective region.
Keywords
Carbon Nanotubes (CNT), Polyvinylidenefluoride (PVDF), Composite Films, Strain Sensor, Defect Detection.- An Improved Cellular Automata-Based Multi Byte ECC
Abstract Views :151 |
PDF Views:4
Authors
V. Nagarajan
1,
V. Kannan
2
Affiliations
1 SASTRA University, Thanjavur, IN
2 Jeppiaar Institute of Technology, Sriperumpudur, Chennai, IN
1 SASTRA University, Thanjavur, IN
2 Jeppiaar Institute of Technology, Sriperumpudur, Chennai, IN
Source
Programmable Device Circuits and Systems, Vol 4, No 15 (2012), Pagination: 788-791Abstract
This paper identifies and resolves the weakness and limitation of existing Cellular Automata (CA)-based byte Error Correcting Code (ECC) and proposes an improved CA-based multi byte ECC which overcomes the identified weakness up to some extent. The code is very much suited from VLSI design viewpoint and requires significantly less hardware and power for decoding compared to the existing techniques employed for Reed–Solomon (RS) Codes. In this paper we are designing the Cellular Automata (CA) based multi byte error correction architecture. Cellular Automata is established for developing bits and bytes Error Correcting Codes. This code is very much suited from Very Large Scale Integration design viewpoint and requires much less hardware and power for decoding. The existing CA based error correcting scheme explains only about the double byte error correction. But this paper explains the error correction possibilities even if more than two errors present.Keywords
Cellular Automata, Error Correcting Code, Multi Byte ECC.- Analysis and Modeling of Hybrid Operational Amplifiers Using Amorphous Silicon Thin Film Transistor
Abstract Views :162 |
PDF Views:1
Authors
G. Prabhakaran
1,
V. Kannan
1
Affiliations
1 Sathyabama University, Chennai-600118, Tamilnadu, IN
1 Sathyabama University, Chennai-600118, Tamilnadu, IN
Source
Programmable Device Circuits and Systems, Vol 3, No 12 (2011), Pagination: 698-704Abstract
A new technique is presented in this paper for the design of a Hybrid TFT operational amplifier made by morphous Silicon thin film transistor and MOSFET which operates at 3V power supply. The OPAMP designed is a two-stage Hybrid TFT OPAMP followed by an output buffer. This Operational Amplifier employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. As compared to the conventional approach, the proposed hybrid operational amplifier result in a higher unity gain amplifier under the same load condition. In this paper we analyze the results of non-inverting amplifier, inverting amplifier, differential amplifier, differentiator and integrator of hybrid operational amplifier, using simulation with Integrated Circuit Emphasis (HSPICE).
Keywords
Operational Amplifier, Hybrid, Non-Inverting Amplifier, Inverting Amplifier, Differential Amplifier, Differentiator, Integrator, Amorphous Silicon Thin Film Transistor, MOSFET, Simulation, HSPICE.- Buried Gate MESFET with Frequency Dependence Transconductance Characteristic
Abstract Views :190 |
PDF Views:1
Authors
Affiliations
1 Sathyabama University, Chennai, IN
2 VLSI Dept, Sathyabama University, Chennai, IN
1 Sathyabama University, Chennai, IN
2 VLSI Dept, Sathyabama University, Chennai, IN
Source
Programmable Device Circuits and Systems, Vol 3, No 12 (2011), Pagination: 705-708Abstract
Analytical model for transconductance ac characteristic of buried-gate GaAs MESFET has obtained by solving continuity equation. When optical fiber is inserted into the active layer of buried-gate GaAs MESFET, the modulated light with frequency is 0.1GHz and Photon absorption coefficient (α) = 1.0x106 m-1 are applied to the buried gate GaAs MESFET through the optical fiber without any deviation. The drain current has calculated from that transconductance is noted. Drain-source current has calculated from the mobility of carriers and absorption coefficient of light. The mobility of the carrier controls the transconductance. The number of holes crossing the Schottky junction calculates the photo voltage. The transconductance and photo voltage characteristic indicate very good performance of the device compared to other devices like MESFET under back illumination and MESFET with front illumination having surface gate. It is highly use full in the nanotechnology and high-speed device.Keywords
Gallium Arsenide Optical Field Effect Transistor GaAs OPFET, Metal Field Effect Transistor (MESFET), Optical Field Effect Transistor (OPFET).- Comparative Analysis of Noise in MODFET and MESFET
Abstract Views :172 |
PDF Views:2
Authors
Affiliations
1 Sathyabama University, Chennai 600119, IN
2 Department of VLSI Design, Sathyabama University, Chennai 600 119, IN
1 Sathyabama University, Chennai 600119, IN
2 Department of VLSI Design, Sathyabama University, Chennai 600 119, IN
Source
Programmable Device Circuits and Systems, Vol 3, No 9 (2011), Pagination: 470-474Abstract
In this paper a comparative analysis of effect of noise in MODFET and MESFET was carried out. Noise is inherent in the device because of various reasons such as leakage current, drifting of charge carriers randomly in the drift space and also because of the charge transportation. There are different kinds of noise which affect the performance of the devices at low and higher frequencies. In this paper, the effect of noise at the input and output of MODFET and MESFET w.r.t to frequency is analyzed. Results are analyzed at 3GHz and 9GHz, because the influence of shot noise will be higher at higher frequencies, whereas flicker noise is higher at lower frequencies. Results show that the effect of noise is more on the MESFET when compared with the MODFET. The effect of noise on the drain characteristics of modfet is also analyzed, where the maximum drain current without the influence of the noise is observed to be 130mA, whereas under the influence of noise, it is observed as 15uA. The work is carried out using PSPICE AD of Orcad 9.1.Keywords
Drain Current, Equivalent Circuit, MODFET, MESFET, Noise.- Design and Analysis of N-Type CNTFET Single Edge Triggered D Flip-Flop Based Shift Registers
Abstract Views :182 |
PDF Views:2
Authors
Affiliations
1 Sathyabama University, Chennai, Tamilnadu-600119, IN
2 Department of VLSI Design, Sathyabama University, Chennai, Tamilnadu, 600119, IN
1 Sathyabama University, Chennai, Tamilnadu-600119, IN
2 Department of VLSI Design, Sathyabama University, Chennai, Tamilnadu, 600119, IN
Source
Programmable Device Circuits and Systems, Vol 3, No 9 (2011), Pagination: 475-480Abstract
This paper enumerates the efficient design and analysis of shift registers like Serial in serial out (SISO), Serial in Parallel out (SIPO), Parallel in parallel out (PIPO), Parallel in serial out (PISO) using N-type CNTFET Single Edge Triggered D Flip-flop. The Flip flop is designed using Ballistic CNTFET (VHDL-AMS model) with the diameter of cnt is 1nm in resistive load inverter logic. There are many issues facing while integrating many number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by considering the carbon nano tube have promising application in the field of electronics. The transient and power analysis are obtained with operating voltage at 0.6V for the single edge triggered D flip-flop and shift registers using system vision tool. The simulation results are presented, and the power consumptions are compared with the conventional MOSFET design. The power consumption of D-Flipflop using mosfet has 9.136uw, whereas for the cntfet based design it was obtained as 0.15uw. Similarly when the shift registers were designed using cntfet power consumption values are 60% better than that of mosfet designs. The comparison of results indicated that the CNTFET based design is capable of efficient power savings.Keywords
CNT, CNTFET, Single Edge Triggered D Flip Flop, Shift Registers, Design Constraints, Circuit Simulation.- Enhanced Optical Effect on the Characteristics of MODFET under Back Side Illumination
Abstract Views :140 |
PDF Views:3
Authors
Affiliations
1 Sathyabama University, Chennai-600118, Tamilnadu, IN
2 St.Josephs Engineering College, Chennai-600118, Tamilnadu, IN
1 Sathyabama University, Chennai-600118, Tamilnadu, IN
2 St.Josephs Engineering College, Chennai-600118, Tamilnadu, IN
Source
Programmable Device Circuits and Systems, Vol 3, No 7 (2011), Pagination: 348-353Abstract
The DC performance of depletion mode AlGaAs/GaAs MODFET under backside optical illumination is studied. A device structure with fiber inserted into the substrate upto the GaAs layer is considered for direct illumination into the GaAs layer. The AlGaAs layer is considered transparent to illumination. The photoconductive effect and the internal reflection effect which increase the 2DEG channel electron concentration are considered. These free electrons generated in the GaAs layer due to both photoconductive effect and the internal reflection effect are collected in 2DEG, there by increasing the source to drain current. The photo generated holes in GaAs layer drift towards the semi-insulating substrate and are capacitively coupled into the grounded source. The sheet concentration , I-V characteristics, transconductance and transfer characteristics of the device AlGaAs/GaAs MODFET have been evaluated and discussed. The I-V characteristics is compared with available experimental data at a particular gate source voltage with and without illumination.
Keywords
Optical Illumination, MODFET, Sheet Concentration, Transconductance, 2DEG.- CNTFET Based SR Flip Flop
Abstract Views :157 |
PDF Views:4
Authors
V. Saravanan
1,
V. Kannan
1
Affiliations
1 Sathyabama University, Chennai, IN
1 Sathyabama University, Chennai, IN
Source
Programmable Device Circuits and Systems, Vol 3, No 8 (2011), Pagination: 423-427Abstract
Carbon Nanotube Field Effect Transistors (CNTFET) are new nano-scaled devices to replace the MOSFET in nano-scale range to provide high performance, very dense and low power circuits. Small size of the MOSFET, below a few tens of nanometres creates the low Trans-conductance, gate oxide leakage, low ON-current, Mobility degradation and increased delay. Problems observed in the MOSFET when size is reduced are avoided in CNTFET, In case of CNTFET carbon nanotube is used as channel and high-k material is used as gate dielectric. In this paper, we present the simulation results of semi-conducting Carbon Nanotube Field Effect Transistors based logic gates and SR Flip Flop. The simulation is done using HSPICE and the current conduction of CNTFET is also analysed.Keywords
Carbon Nanotube, CNTFET, NAND Gate, SR Flip Flop.- Effect of CNTFET on 4 to 2 Compressor
Abstract Views :155 |
PDF Views:3
Authors
Affiliations
1 Sathyabama University, Chennai, Tamilnadu, IN
2 Jeppiaar Institute of Technology, Kunnam, Tamilnadu, IN
1 Sathyabama University, Chennai, Tamilnadu, IN
2 Jeppiaar Institute of Technology, Kunnam, Tamilnadu, IN
Source
Digital Signal Processing, Vol 4, No 6 (2012), Pagination: 254-259Abstract
This paper enumerates the efficient design and Abstract---This paper enumerates the efficient design and analysis of a 4 to 2 compressor using Full Adder cell. The Full Adder is designed using Stanford University CNTFET model and proposed 10nm CNTFET model. There are many issues facing while integrating more number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by Considering the carbon nano tube have promising application in the field of electronics. The carbon nanotube is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage at 0.9V. The simulation results are presented and the analyses are compared with circuits designed using 32nm MOSFET. The comparison of results indicated that the proposed 10nm CNTFET based design is more efficient in power savings and speed.
Keywords
CNT, CNTFET, Full Adder Cell, Compressor, Design Constraints and Circuit Simulation.- The Buried Gate Mesfet with Turning on Characteristic
Abstract Views :163 |
PDF Views:3
Authors
Affiliations
1 ECE, Sathyabama University, Chennai, IN
2 VLSI Dept, Sathyabama University, Chennai, IN
1 ECE, Sathyabama University, Chennai, IN
2 VLSI Dept, Sathyabama University, Chennai, IN
Source
Journal of Advances in Engineering Sciences, Vol 3, No 2 (2010), Pagination: 49-52Abstract
The buried-gate GaAs MESFET with front illumination using turning ON channel current been analyzed by solving continuity equation. This analysis includes the ion implanted buried-gate process. At time 't' is equal to zero, the light through the optical fiber is turning 'ON' has been considered. The channel current has been evaluated and discussed. Buried-gate optical field effect transistor (OPFET) will be highly suitable for microwave communication.- A Novel and Hybrid Secure Digital Image Watermarking Framework Through sc-LWT-SVD
Abstract Views :206 |
PDF Views:0
Authors
Affiliations
1 Department of CSE, Bharath University, Chennai 600073, IN
2 Department of CSE, VBIT, Hyderabad, IN
1 Department of CSE, Bharath University, Chennai 600073, IN
2 Department of CSE, VBIT, Hyderabad, IN
Source
Indian Journal of Science and Technology, Vol 9, No 23 (2016), Pagination:Abstract
Background: In the recent internet world, the watermarking security dispute has incurring design challenges on watermarking techniques. This article has anticipated a robust and secure watermarking pattern, based on SC-LWT-SVD which is projected so as to challenge the numerous serious watermarking security disputes, i.e., copyright protection through encryption, unsanctioned interpretation, false positive recognition, and numerous prerogatives of tenure complications. Methods: Initially SC-LWT is accomplished to split the input values, in order to acquire approximate coefficients. The SVD is applied on LWT coefficients to originate singular constants. Findings: The proposed SC–LWT– SVD constructed watermarking arrangement is verified with numerous malicious and un-malicious outbreaks and the experimental outcomes illustrate that it comprehends the security prerequisites which resolves false positive detection and copyright protection. Furthermore, this pattern is deliberated to blind scheme. Application: The simulation model is accustomed to verify the viability of the anticipated pattern and its forcefulness in contradiction of numerous outbreaks and to link with some earlier systems.Keywords
Digital Image Watermarking, False Positive Detection, LWT, Singular Value Decomposition (SVD), Sparse Coding.Full Text
- A Study on 'The Perception of the Role, Played by Internet Applications on Human Abilities
Abstract Views :153 |
PDF Views:6
Authors
Source
International Journal of Innovative Research and Development, Vol 1, No 4 (2012), Pagination: 365-375Abstract
The internet and its myriad applications like the email, chat, social networking have profoundly impacted our daily lives. The aim of the paper is to study the difference in perceptions of the Indian Military Officers and their Wives on the role of internet applications on human abilities and relationship of the difference in perceptions with regards to gender and age. The method used is quantitative research and the population comprised of Indian Military Officers and their Wives. A random sample had been taken from the said population from various Military establishments throughout India and at the Defence Services Staff College. The survey instrument was a questionnaire through which data were obtained from the sample to seek their inputs on the use and impact of the internet applications on human abilities. Based on literature review it is seen that the internet due to its Immense utility has improved our abilities and therefore, it needs to be seen if there exists any difference in perceptions. Thus the hypotheses for the study has been formulated as "The perception of Indian Military Officers and their wives on the role played by internet applications on human abilities is judged similarly by the opposite sexes and by persons from different age groups". The results have supported the hypotheses and show that the perceptions on the role of intemet applications are seen similarly by both sexes and different age groups.Keywords
Internet, Abilities, Internet Applications, Convenience, PerceptionsFull Text
- Implementation of Lean Manufacturing Practices and its Impact on Productivity in Coimbatore Foundries
Abstract Views :179 |
PDF Views:0
Authors
Affiliations
1 Kumaraguru College of Technology, Coimbatore, Tamil Nadu, IN
1 Kumaraguru College of Technology, Coimbatore, Tamil Nadu, IN