Informatics Publishing Limited

P. Penchala Reddy ¹, V. Thrimurthulu ¹, K. Jagadeesh Kumar ¹

Affiliations
1 Dept.of ECE, CREC, Tirupathi, A.P., IN

Abstract

Increasing need of high security in communication led to the development of several cryptographic algorithms hence sending data securely over a transmission link is critically important in many applications. NIST in the beginning selected Rijndael within October 2000 and formal adoption as being the AES standard started in December 2001. FIPS PUB 197 explains a 128-bit block cipher making Ause of a 128, 192, or 256-bit key. In cryptography, modes of operation enable the repeated and secure use of a block cipher under a single key. This paper presents implementation of multi mode AES algorithm with three modes ECB, CBC and CTR modes. All these three modes are implemented with 128-bit plain text and 128 bit, 192 bit and 256 bit key lengths. Each program results are verified with ModelSim PE and are synthesized in Xilinx ISE 9.2i. These results are also useful for implementing hardware.

Keywords

Cryptography, Rijndael, Mode Selection Logic, Key Expansion Block, Cipher Block, Decipher Block.

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Billu Balaji ¹, V. Thrimurthulu ², L. Mihira Priya ³

Affiliations
1 Dept of VLSISD, CR Engineering College, Tirupati, Chittor, AP, IN
2 Dept of ECE, CR Engineering College, Tirupati, Chittor, AP, IN
3 Dept of Electronics, SJD&PG College, Hyderabad, TS, IN

Abstract

Process variation is an difficulty in designing reliable CMOS mixed signal systems with high yield. To minimize the variation in voltage gain due to variations in process, supply voltage, and temperature for common trans conductance-based amplifiers, we present a new compensation method based on statistical feedback of process information. We further apply our scheme to two well known amplifier topologies in the sun-micron CMOS process as design examples-an inductive degenerated low-noise amplifier (LNA) and a common source amplifier (CSA). The proposed method improves the variation in S21 of an inductively degenerated cascade LNA from 8.75% to 1.27%, which is a reduction in variation of 85%. The presented scheme is also robust over variations in supply voltage, temperature, and process conditions. The compensation method presented can be utilized to stabilize the gain of a wide variety of amplifiers.

Keywords

CMOS Analog Integrated Circuits, Process Compensation, Process Variation, Self-Biasing.

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