Edwar Jacinto ¹, Holman Montiel ¹, Fernando Martinez ¹

Affiliations
1 Technological Faculty, District University Francisco Jose de Caldas, Bogota D.C., CO

Abstract

Objectives: This paper shows an optimized code for light-weight cipher algorithms, attempting to keep the balance between the use of resources and the communication speed. Methods/Analysis: A real performance analysis is applied to the cryptographic algorithm CLEFIA, under the standards by ISO/IEC 29192-2, by means of a code optimization for key scheduling through bit-oriented instructions. It is used the Freescale KL25Z development board for the measure of response times and the structural blocks’ execution times for the cipher algorithm. Findings: In this paper a bit-level optimization was sought over some operative structures of the algorithm, taking advantage of the 32-bit architecture in the development platform, generating this way a better response time for the application and an increase of the Throughput performance regarding the reference code by SONY. Novelty/Improvement: This application was developed so it can be used by many platforms into any electronic application, which requires an encryption process, where the use of a PC is not worthy because of the size and cost.

Keywords

Cipher Algorithm, ISO/IEC 29192, Lightweight Algorithm.

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Edilberto Carlos Vivas Gonzalez ¹, Diego Mauricio Rivera ¹, Edwar Jacinto ¹

Affiliations
1 Universidad Libre, Universidad Pedagogica Nacional and Universidad Distrital Bogota D.C., Bogota, CO

Abstract

Objectives: The educational implementation of code generation software for FPGA device is presented. The objective is to allow the students to develop implementations without knowing the structure of the programmable logics device, or any hardware description language. Methods: A software tool was developed for this purpose. In the user's interface of the tool, the transference function of the controller or digital filter must be entered, and then the code VHDL will be automatically generated in a standard format, compatible with any programmable logics device. Findings: It was found that the possibility that students might have by implementing a controller, or a higher-order system without making a complex code makes that the learning process speeds up, and that the student faces specific problems related to digital control and signals processing, leaving aside the restrictions given by the difficulties in the use of the hardware's description language, as well as the required knowledge of the devices structure. The use of the tool allows that students develop their laboratory practices generating digital dynamic systems in a high level, which allows avoiding potential errors in their implementations. Besides the possibilities in the industrial level, the tool is capable of being used by students of Engineering without knowledge in hardware programming, which study topics related to control, but not specialized in topics related to implementation. Application: Results linked to learning in some engineering classes with and without the use of the tool are shown at the end of this paper.

Keywords

Control Systems, Education, Engineering Teaching, FPGA Code Generation, Signal Processing.

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